Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 221

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 112. ESPI Control Register (ESPICTL)
BITS
FIELD
RESET
R/W
ADDR
PS025011-1010
ESPI Control Register
DIRQE
R/W
7
0
TEOF—Transmit End of Frame
This bit is used in MASTER mode to indicate that the data in the transmit data register is
the last byte of the transfer or frame. When the last byte has been sent SS (and SSV) will
change state and TEOF will automatically clear.
0 = The data in the transmit data register is not the last character in the message.
1 = The data in the transmit data register is the last character in the message.
SSV—Slave Select Value
When SSIO = 1, writes to this register will control the value output on the SS pin. For
more details, see SSMD field of the
The ESPI Control register (see
receive operations.
DIRQE—Data Interrupt Request Enable
This bit is used to disable or enable data (TDRE and RDRNE) interrupts. Disabling the
data interrupts is needed to control data transfer by polling. Error interrupts are not
disabled. To block all ESPI interrupt sources, clear the ESPI interrupt enable bit in the
Interrupt Controller.
0 = TDRE and RDRNE assertions do not cause an interrupt. 
1 = TDRE and RDRNE assertions will cause an interrupt.
ESPIEN1, ESPIEN0—ESPI Enable and Direction Control
00 = ESPI block is disabled. 
01 = Receive Only Mode.
Use this setting if controlling data transfer by software polling of TDRE
and RDRNE. The TUND, COL, ABT, and ROVR bits will cause an interrupt.
TUND, COL, ABT, and ROVR will also cause interrupts. Use this setting when 
controlling data transfer via interrupt handlers.
BRG may be used as a general purpose timer by setting BRGCTL = 1.
Use this setting in SLAVE mode if software application is receiving data but not
sending. TDRE will not assert. Transmitted data will be all 1’s. Not valid in 
MASTER mode since Master must source data to drive the transfer.
ESPIEN1
R/W
6
0
BRGCTL
R/W
5
0
P R E L I M I N A R Y
Table
PHASE
R/W
4
0
ESPI Mode Register
112) configures the ESPI for transmit and 
F62H
CLKPOL
R/W
3
0
Z8 Encore! XP
Enhanced Serial Peripheral Interface
on page 209.
WOR
R/W
2
0
Product Specification
MMEN
R/W
1
0
®
F1680 Series
ESPIEN0
R/W
0
0
207