Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 235

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
Master Transactions
The following sections describe Master Read and Write transactions to both 7-bit and 
10-bit slaves.
Master Arbitration
If a Master loses arbitration during the address byte it releases the SDA line, switches to
SLAVE mode and monitors the address to determine if it is selected as a Slave. If a Master
loses arbitration during the transmission of a data byte, it releases the SDA line and waits
for the next
The Master detects a loss of arbitration when a 1 is transmitted but a 0 is received from the
bus in the same bit-time. This loss occurs if more than one Master is simultaneously
accessing the bus. Loss of arbitration occurs during the address phase (two or more
Masters accessing different slaves) or during the data phase, when the masters are
attempting to Write different data to the same Slave.
When a Master loses arbitration, the software is informed by means of the Arbitration Lost
interrupt. The software can repeat the same transaction at a later time.
A special case can occur when a Slave transaction starts just before the software 
attempts to start a new master transaction by setting the
the state machine enters its Slave states before the
the I
receives/transmits data, the
asserted. The software can minimize the chance of this instance occurring by checking 
the
address match does not occur, the Arbitration Lost interrupt will not occur, and the 
START
the I
Master Address-Only Transactions
It is sometimes preferable to perform an address-only transaction to determine 
if a particular slave device is able to respond. This transaction can be performed by
monitoring the
written to the I2CDATA Register and the
is set, the
communicate. The
transaction without transferring data. For a 10-bit slave address, if the first address 
byte is acknowledged, the second address byte should also be sent to determine 
if the preferred Slave is responding.
Another approach is to set both the
After both bits have been cleared (7-bit address has been sent and transaction is complete),
the
ACK
BUSY
2
2
C controller will not arbitrate. If a Slave address match occurs and the I
C bus is no longer busy.
bit will not be cleared. The I
bit can be read to determine if the Slave has acknowledged. For a 10-bit Slave, set
bit in the I2CSTATE Register before initiating a Master transaction. If a slave
ACK
STOP
bit in the I2CSTATE Register determines if the slave is able to
ACKV
or
STOP
START
bit in the I2CSTATE Register after the address has been 
bit must be set in the I2CCTL Register to terminate the
START
P R E L I M I N A R Y
condition.
bit is cleared and an Arbitration Lost interrupt is
STOP
2
C controller will initiate the master transaction after
START
and
START
bit has been set. After the
START
bits (for sending a 7-bit address).
Z8 Encore! XP
START
bit is set, and as a result 
bit. In this case, 
Product Specification
I2C Master/Slave Controller
®
F1680 Series
ACKV
2
C controller
bit 
221