AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 674

IC ARM9 MCU 208 PQFP

AT91RM9200-QU-002

Manufacturer Part Number
AT91RM9200-QU-002
Description
IC ARM9 MCU 208 PQFP
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91RM9200-QU-002

Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Processor Series
AT91Rx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, EBI, I2S, SPI, UART, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
122
Number Of Timers
10 bit
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
Minimum Operating Temperature
- 40 C
Eeprom Memory
0 Bytes
Input Output
122
Interface
EBI/EMI, UART/USART
Ios
122
Memory Type
ROM
Number Of Bits
32
Package Type
208-pin PQFP
Programmable Memory
128K Bytes
Timers
3-16-bit
Voltage, Range
1.65-1.95 V
Cpu Family
91R
Device Core
ARM920T
Device Core Size
32b
Frequency (max)
180MHz
Total Internal Ram Size
16KB
# I/os (max)
122
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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41.4.11
41.5
41.5.1
41.5.2
41.6
41.6.1
41.6.2
674
PIO
PMC
AT91RM9200
Data write operation and number of bytes
NWAIT activity depends on use of PC6
Output Data Status Register is always Read/Write
Constraints on the Master Clock selection sequence
MCKRDY does not rise in some cases
Problem Fix/Workaround
It consists in doing a software reset if RXRDY = 1 after the STOP_COMMAND. This flag indi-
cates that the MMCI receives more data than the PDC has been settle to transfer. After this soft
reset the MCI_CR, MCI_MR, MCI_DTOR, MCI_SDCR need to be reassigned.
The Data Write operation with a number of bytes less than 12 is impossible.
Problem Fix/Workaround
The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The
BLKLEN or BCNT field are used to specify the real count number.
NWAIT activity depends on use of PC6. The PC6 line multiplexes with the NWAIT function. As
the PIO Controller is transparent in input, the level on the PC6 line has direct impact on the
behavior of the EBI. In particular, driving the PC6 line to 0 might lead to a deadlock of the
system.
Problem Fix/Workaround
Use PC6 carefully. In general, it is recommended to not use PC6 and to make sure the pull-up is
enabled.
The programming of the register PIO_OWSR has no effect on the read/write features of
PIO_ODSR, which is always read/write accessible.
Problem Fix/Workaround
None.
The PMC_MCKR register must not be programmed in a single write operation.
Problem Fix/Workaround
The preferred programming sequence for the PMC_MCKR register is as follows:
An exception to this sequence occurs when the processor clock frequency is greater than the
master clock frequency. In this case, the PRES field should be written first.
When re-programming the Master Clock Register, if both fields PRES and CSS are written with
the same values as the ones already stored, or if both fields are written with different values than
1. Program the CSS field in the PMC_MCKR.
2. Wait for the MCKRDY bit to be set in the PMC_SR register.
3. Program the PRES field (in the PMC_MCKR).
1768I–ATARM–09-Jul-09

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