AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 610

• Manufacturer Part Number: AT91RM9200-QU-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QU-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91Rx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, UART, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 122
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 122
• Interface: EBI/EMI, UART/USART
• Ios: 122
• Memory Type: ROM
• Number Of Bits: 32
• Package Type: 208-pin PQFP
• Programmable Memory: 128K Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.65-1.95 V
• Cpu Family: 91R
• Device Core: ARM920T
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 16KB
• # I/os (max): 122
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

36.5.5
610
AT91RM9200
Address Checking
Table 36-4.
Whether or not a frame is stored depends on what is enabled in the network configuration regis-
ter, the contents of the specific address and hash registers and the frame destination address. In
this implementation of the MAC the frame source address is not checked.
A frame is not copied to memory if the MAC is transmitting in half-duplex mode at the time a des-
tination address is received.
The hash register is 64 bits long and takes up two locations in the memory map.
There are four 48-bit specific address registers, each taking up two memory locations. The first
location contains the first four bytes of the address; the second location contains the last two
bytes of the address stored in its least significant byte positions. The addresses stored can be
specific, group, local or universal.
Ethernet frames are transmitted a byte at a time, LSB first. The first bit (i.e., the LSB of the first
byte) of the destination address is the group/individual bit and is set one for multicast addresses
and zero for unicast. This bit corresponds to bit 24 of the first word of the specific address regis-
ter. The MSB of the first byte of the destination address corresponds to bit 31 of the specific
address register.
The specific address registers are compared to the destination address of received frames once
they have been activated. Addresses are deactivated at reset or when the first byte [47:40] is
written and activated or when the last byte [7:0] is written. If a receive frame address matches an
active address, the local match signal is set and the store frame pulse signal is sent to the DMA
block via the HCLK synchronization block.
A frame can also be copied if a unicast or multicast hash match occurs, it has the broadcast
address of all ones, or the copy all frames bit in the network configuration register is set.
The broadcast address of 0xFFFFFFFF is recognized if the no broadcast bit in the network con-
figuration register is zero. This sets the broadcast match signal and triggers the store frame
signal.
The unicast hash enable and the multicast hash enable bits in the network configuration register
enable the reception of hash matched frames. So all multicast frames can be received by setting
all bits in the hash register.
Bit
30
29
28
27
26
25
24
23
22:11
10:0
Received Buffer Descriptor List
Function
Multicast hash match
Unicast hash match
External address (optional)
Unknown source address (reserved for future use)
Local address match (Specific address 1 match)
Local address match (Specific address 2 match)
Local address match (Specific address 3 match)
Local address match (Specific address 4 match)
Reserved; written to 0
Length of frame including FCS
1768I–ATARM–09-Jul-09