AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 660

IC ARM9 MCU 208 PQFP

AT91RM9200-QU-002

Manufacturer Part Number
AT91RM9200-QU-002
Description
IC ARM9 MCU 208 PQFP
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91RM9200-QU-002

Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Processor Series
AT91Rx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, EBI, I2S, SPI, UART, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
122
Number Of Timers
10 bit
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
Minimum Operating Temperature
- 40 C
Eeprom Memory
0 Bytes
Input Output
122
Interface
EBI/EMI, UART/USART
Ios
122
Memory Type
ROM
Number Of Bits
32
Package Type
208-pin PQFP
Programmable Memory
128K Bytes
Timers
3-16-bit
Voltage, Range
1.65-1.95 V
Cpu Family
91R
Device Core
ARM920T
Device Core Size
32b
Frequency (max)
180MHz
Total Internal Ram Size
16KB
# I/os (max)
122
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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38.4
38.4.1
Table 38-11. ETM Timing Characteristics
38.4.2
660
Symbol
1/(t
t
t
t
ETM
ETM
ETM
ETM
CPTCLK
CHTCLK
CLTCLK
CPTCLK
0
1
2
3
ETM Timings
)
AT91RM9200
Timings Data
Design Considerations
Parameter
Trace Clock Frequency
Trace Clock Period
TCLK High Half-period
TCLK Low Half-period
Data Signals Out Valid
before TCLK Rising Edge
Data Signals Out Valid after
TCLK Rising Edge
Data Signals Out Valid
before TCLK Falling Edge
Data Signals Out Valid after
TCLK Falling Edge
Table 38-11
“Conditions and Timings Computation” on page
Figure 38-11. ETM Signals
When designing a PCB, it is important to keep the differences between trace length of ETM sig-
nals as small as possible to minimize skew between them. In addition, crosstalk on the trace port
must be kept to a minimum as it can cause erroneous trace results. Stubs on these traces can
cause unpredictable responses, thus it is recommended to avoid stubs on the trace lines.
The TCLK line should be series-terminated as close as possible to the microcontroller pins.
The maximum capacitance presented by the trace connector, cabling and interfacing logic must
be less than 15 pF.
TPK[15:0]
TPS[2:0]
TSYNC
TCLK
shows timings relative to operating condition limits defined in the section
Conditions
C = 0 pF
C
C = 0 pF
C
DATA
DATA
derating
derating
t
CLTCLK
t
t
CPTCLK
CPTCLK
t
t
t
t
CHTCLK
CHTCLK
CLTCLK
CLTCLK
11.56
0.044
0.044
Min
/2 + 0.02
/2 - 0.02
- 1.06
- 0.51
- 0.49
- 1.03
t
CPTCLK
639.
1/(2
t
CHTCLK
2
x
Typ
x
t
CPPCK
t
CPPCK
)
86.54
Max
1768I–ATARM–09-Jul-09
Units
ns/pF
ns/pF
MHz
ns
ns
ns
ns
ns
ns
ns
38.1.1

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