AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 228

IC ARM9 MCU 208 PQFP

AT91RM9200-QU-002

Manufacturer Part Number
AT91RM9200-QU-002
Description
IC ARM9 MCU 208 PQFP
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91RM9200-QU-002

Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Processor Series
AT91Rx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, EBI, I2S, SPI, UART, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
122
Number Of Timers
10 bit
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
Minimum Operating Temperature
- 40 C
Eeprom Memory
0 Bytes
Input Output
122
Interface
EBI/EMI, UART/USART
Ios
122
Memory Type
ROM
Number Of Bits
32
Package Type
208-pin PQFP
Programmable Memory
128K Bytes
Timers
3-16-bit
Voltage, Range
1.65-1.95 V
Cpu Family
91R
Device Core
ARM920T
Device Core Size
32b
Frequency (max)
180MHz
Total Internal Ram Size
16KB
# I/os (max)
122
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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3
• PAGES: Page Size
This field defines the page size handling and the page size.
• OEL: Output Enable Latency
This field defines the number of idle cycles inserted after each level change on the BFOE output enable signal. OEL range
is 1 to 3.
• BAAEN: Burst Address Advance Enable
0: The burst clock is enabled to increment the burst address or, disabled to remain at the same address.
1: The burst clock is continuous and the burst address advance is controlled with the BFBAA pin.
• BFOEH: Burst Flash Output Enable Handling
0: No burst resume in Burst Mode. When the BFC is deselected, this causes an irreversible break of the burst. A new burst
will be initiated for the next access.
1: Burst resume. When the BFC is deselected, the burst is suspended. It will be resumed if the next access is sequential to
the last one.
• MUXEN: Multiplexed Bus Enable
0: The address and data busses operate independently.
1: The address and data busses are multiplexed. Actually, the address is presented on both the data bus and the address
bus when the BFAVD signal is asserted.
• RDYEN: Ready Enable Mode
0: The BFRDY input signal at the BFC input interface is ignored.
1: The BFRDY input signal is used as an indicator of data availability in the next cycle.
228
0
0
0
0
1
1
1
1
AT91RM9200
Pages
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Page Size
No page handling. The Ready Signal (BFRDY) is sampled to check if the next
data is available.
16 bytes page size
32 bytes page size
64 bytes page size
128 bytes page size
256 bytes page size
512 bytes page size
1024 bytes page size
1768I–ATARM–09-Jul-09

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