T89C51CC01CA-7CTIM Atmel, T89C51CC01CA-7CTIM Datasheet - Page 51

• Manufacturer Part Number: T89C51CC01CA-7CTIM
• Description: IC 8051 MCU FLASH 32K 64BGA
• Manufacturer: Atmel
• Series: AT89C CANr

Specifications of T89C51CC01CA-7CTIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• For Use With: AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: T89C51CC01CA7CTIM

Serial I/O Port
Figure 27. Serial I/O Port Block Diagram
Figure 28. Framing Error Block Diagram
4129N–CAN–03/08
Framing Error Detection
TXD
RXD
The T89C51CC01 I/O serial port is compatible with the I/O serial port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as a
Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes
(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously
and at different baud rates
Serial I/O port includes the following enhancements:
•
•
Framing bit error detection is provided for the three asynchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register.
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register bit is set.
The software may examine the FE bit after each reception to check for data errors.
Once set, only software or a reset clears the FE bit. Subsequently received frames with
valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the
stop bit instead of the last data bit (See Figure 29. and Figure 30.).
SM0/FE
SMOD1
Framing error detection
Automatic address recognition
Transmitter
SMOD0
SBUF
SM1
SM2
-
Mode 0 Transmit
IB Bus
Write SBUF
SCON reg
RI
REN
Set FE bit if stop bit is 0 (framing error)
SM0 to UART mode control
POF
To UART framing error control
TI
TB8
GF1
RB8
GF0
Shift register
Receive
Receiver
SBUF
PD
TI
IDL
RI
Read SBUF
Load SBUF
Serial Port
Interrupt
Request
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