T89C51CC01CA-7CTIM Atmel, T89C51CC01CA-7CTIM Datasheet

IC 8051 MCU FLASH 32K 64BGA

T89C51CC01CA-7CTIM

Manufacturer Part Number
T89C51CC01CA-7CTIM
Description
IC 8051 MCU FLASH 32K 64BGA
Manufacturer
Atmel
Series
AT89C CANr

Specifications of T89C51CC01CA-7CTIM

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-BGA
For Use With
AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
T89C51CC01CA7CTIM

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
T89C51CC01CA-7CTIM
Manufacturer:
Atmel
Quantity:
10 000
Features
1.
80C51 Core Architecture
256 Bytes of On-chip RAM
1K Bytes of On-chip XRAM
32K Bytes of On-chip Flash Memory
Boot Code Section with Independent Lock Bits
2K Bytes of On-chip Flash for Bootloader
In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability
2K Bytes of On-chip EEPROM
Erase/Write Cycle: 100K
14-sources 4-level Interrupts
Three 16-bit Timers/Counters
Full Duplex UART Compatible 80C51
Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz)
Five Ports: 32 + 2 Digital I/O Lines
Five-channel 16-bit PCA with:
Double Data Pointer
21-bit Watchdog Timer (7 Programmable Bits)
A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs
Full CAN Controller:
On-chip Emulation Logic (Enhanced Hook System)
Power Saving Modes:
– Data Retention: 10 Years at 85° C
– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture
– Fully Compliant with CAN Rev2.0A and 2.0B
– Optimized Structure for Communication Management (Via SFR)
– 15 Independent Message Objects:
– Supports:
– 1-Mbit/s Maximum Transfer Rate at 8 MHz
– Readable Error Counters
– Programmable Link to On-chip Timer for Time Stamping and Network
– Independent Baud Rate Prescaler
– Data, Remote, Error and Overload Frame Handling
– Idle Mode
– Power-down Mode
Erase/Write Cycle: 100K
Synchronization
Each Message Object Programmable on Transmission or Reception
Individual Tag and Mask Filters up to 29-bit Identifier/Channel
8-byte Cyclic Data Register (FIFO)/Message Object
16-bit Status and Control Register/Message Object
16-bit Time-Stamping Register/Message Object
CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
Object
Access to Message Object Control and Data Registers Via SFR
Programmable Reception Buffer Length Up To 15 Message Objects
Priority Management of Reception of Hits on Several Message Objects at the
Same Time (Basic CAN Feature)
Priority Management for Transmission
Message Object Overrun Interrupt
Time Triggered Communication
Autobaud and Listening Mode
Programmable Automatic Reply Mode
At BRP = 1 sampling point will be fixed.
(1)
Crystal Frequency in X2 Mode
Enhanced 8-bit
Microcontroller
with CAN
Controller and
Flash Memory
T89C51CC01
AT89C51CC01
Rev. 4129N–CAN–03/08
1

Related parts for T89C51CC01CA-7CTIM

T89C51CC01CA-7CTIM Summary of contents

Page 1

Features • 80C51 Core Architecture • 256 Bytes of On-chip RAM • 1K Bytes of On-chip XRAM • 32K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85° C Erase/Write Cycle: 100K • Boot Code Section with ...

Page 2

Power Supply 5.5V • Temperature Range: Industrial (-40° to +85°C) • Packages: VQFP44, PLCC44 Description Block Diagram XTAL1 XTAL2 ALE PSEN Notes analog Inputs/8 Digital I/O 2. 2-Bit I/O Port A/T89C51CC01 2 ...

Page 3

Pin Configuration 4129N–CAN–03/08 P1.4/AN4/CEX1 7 P1.5/AN5/CEX2 8 P1.6/AN6/CEX3 9 P1.7/AN7/CEX4 P3.0/RxD 12 PLCC44 P3.1/TxD 13 P3.2/INT0 14 P3.3/INT1 15 P3.4/T0 16 P3.5/ P1.4/AN4/CEX1 1 P1.5/AN5/CEX2 2 P1.6/AN6/CEX3 3 P1.7/AN7/CEX4 4 ...

Page 4

I/O Configurations Port 1, Port 3 and Port 4 Port 0 and Port 2 A/T89C51CC01 4 Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch" signal initiates ...

Page 5

Read-Modify-Write Instructions 4129N–CAN–03/08 Figure 2. Port 0 Structure ADDRESS LOW/ DATA READ LATCH INTERNAL BUS D Q P0.X LATCH WRITE TO LATCH READ PIN Notes: 1. Port 0 is precluded from use as general-purpose I/O Ports when used as address/data ...

Page 6

Quasi-Bidirectional Port Operation A/T89C51CC01 6 Table 1. Read-Modify-Write Instructions Instruction Description ANL logical AND ORL logical OR XRL logical EX-OR JBC jump if bit = 1 and clear bit CPL complement bit INC increment DEC decrement DJNZ decrement and jump ...

Page 7

Figure 4. Internal Pull-Up Configurations 2 Osc. PERIODS OUTPUT DATA INPUT DATA READ PIN Note: Port 2 p1 assists the logic-one output for memory bus cycles. VCC VCC VCC p2 p1(1) p3 P1.x P2.x P3.x P4 ...

Page 8

SFR Mapping Table 2. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer Data Pointer Low byte DPL 82h LSB of DPTR Data Pointer High byte DPH ...

Page 9

Table 4. Timers SFRs (Continued) Mnemonic Add Name Timer/Counter 2 T2CON C8h control Timer/Counter 2 T2MOD C9h Mode Timer/Counter 2 RCAP2H CBh Reload/Capture High byte Timer/Counter 2 RCAP2L CAh Reload/Capture Low byte Watchdog Timer WDTRST A6h Reset Watchdog Timer WDTPRG ...

Page 10

Table 6. PCA SFRs (Continued) Add Name Mnemonic CCAP0L EAh PCA Compare Capture Module 0 L CCAP1L EBh PCA Compare Capture Module 1 L CCAP2L ECh PCA Compare Capture Module 2 L CCAP3L EDh PCA Compare Capture Module 3 L ...

Page 11

Table 9. CAN SFRs (Continued) Mnemonic Add Name CAN Enable CANEN1 CEh Channel byte 1 CAN Enable CANEN2 CFh Channel byte 2 CAN General CANGIE C1h Interrupt Enable CAN Interrupt CANIE1 C2h Enable Channel byte 1 CAN Interrupt CANIE2 C3h ...

Page 12

Table 9. CAN SFRs (Continued) Mnemonic Add Name CAN Identifier Tag byte 1(Part A) CANIDT1 BCh CAN Identifier Tag byte 1(PartB) CAN Identifier Tag byte 2 (PartA) CANIDT2 BDh CAN Identifier Tag byte 2 (PartB) CAN Identifier Tag byte 3(PartA) ...

Page 13

Table 10. Other SFRs Mnemonic Add Name FCON D1h Flash Control EECON D2h EEPROM Contol Table 11. SFR Mapping (1) 0/8 1/9 IPL1 CH F8h xxxx x000 0000 0000 B F0h 0000 0000 IEN1 CL E8h xxxx x000 0000 0000 ...

Page 14

Clock Description A/T89C51CC01 14 The T89C51CC01 core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power ...

Page 15

Figure 5. Clock CPU Generation Diagram Hardware byte XTAL1 XTAL2 PD PCON.1 ÷ 2 ÷ CKCON.0 CANX2 CKCON.7 4129N–CAN–03/08 X2B PCON.0 On RESET IDL X2 CKCON.0 0 ÷ ÷ 2 ÷ ...

Page 16

Figure 6. Mode Switching Waveforms XTAL1 XTAL1/2 X2 bit CPU clock STD Mode Note: In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a ...

Page 17

Register 4129N–CAN–03/08 Table 12. CKCON Register CKCON (S:8Fh) Clock Control Register CANX2 WDX2 PCAX2 Bit Bit Number Mnemonic Description (1) CAN clock 7 CANX2 Clear to select 6 clock periods per peripheral clock cycle. Set to select ...

Page 18

Power Management Reset Pin At Power-up (Cold Reset) A/T89C51CC01 18 Two power reduction modes are implemented in the T89C51CC01: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction ...

Page 19

Warm Reset Watchdog Reset Reset Recommendation to Prevent Flash Corruption Idle Mode Entering Idle Mode Exiting Idle Mode 4129N–CAN–03/08 To achieve a valid reset, the reset signal must be maintained for at least 2 machine cycles (24 oscillator clock periods) ...

Page 20

Power-down Mode Entering Power-down Mode Exiting Power-down Mode A/T89C51CC01 20 of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Idle mode. The general-purpose flags (GF1 and GF0 in PCON register) may be ...

Page 21

Figure 9. Power-down Exit Waveform Using INT1:0# INT1:0# OSC Active phase 4129N–CAN–03/08 Power-down phase Oscillator restart phase 2. Generate a reset. – A logic high on the RST pin clears PD bit in PCON register directly and asynchronously. This starts ...

Page 22

Registers A/T89C51CC01 22 Table 15. PCON Register PCON (S:87h) – Power configuration Register SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode 1, ...

Page 23

Data Memory 4129N–CAN–03/08 The T89C51CC01 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: • the lower 128 Bytes RAM segment. • the upper 128 Bytes RAM segment. • the expanded 1024 ...

Page 24

Internal Space Lower 128 Bytes RAM Upper 128 Bytes RAM Expanded RAM A/T89C51CC01 24 The lower 128 Bytes of RAM (see Figure 11) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 Bytes ...

Page 25

External Space Memory Interface External Bus Cycles 4129N–CAN–03/08 The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD, WR, and ALE). Figure 13 shows the structure of the external ...

Page 26

A/T89C51CC01 26 Figure 14. External Data Read Waveforms CPU Clock ALE DPL Notes: 1. signal may be stretched using M0 bit in AUXR register When executing MOVX @Ri instruction, P2 outputs ...

Page 27

Dual Data Pointer Description Application 4129N–CAN–03/08 The T89C51CC01 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR 0 and DPTR 1 are seen by the ...

Page 28

Registers A/T89C51CC01 28 Table 18. PSW Register PSW (S:D0h) Program Status Word Register Bit Bit Number Mnemonic Description Carry Flag 7 CY Carry out from bit 1 of ALU operands. Auxiliary Carry Flag 6 ...

Page 29

Bit Bit Number Mnemonic Description Internal/External RAM (00h - FFh) access using MOVX @ Ri/@ DPTR 1 EXTRAM 0 - Internal XRAM access using MOVX @ Ri/@ DPTR External data memory access. Disable/Enable ALE ALE ...

Page 30

EEPROM Data Memory Write Data in the Column Latches Programming Read Data A/T89C51CC01 30 The 2-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/XRAM memory space and is selected by setting control bits in ...

Page 31

Examples 4129N–CAN–03/08 ;*F************************************************************************* ;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_rd_eeprom_byte: ; Save and clear EA MOV EECON, ...

Page 32

Registers A/T89C51CC01 32 Table 21. EECON Register EECON (S:0D2h) EEPROM Control Register EEPL3 EEPL2 EEPL1 Bit Bit Number Mnemonic Description Programming Launch command bits 7-4 EEPL3-0 Write 5Xh followed by AXh to EEPL to launch the programming. ...

Page 33

Program/Code Memory 4129N–CAN–03/08 The T89C51CC01 implement 32K Bytes of on-chip program/code memory. Figure 17 shows the partitioning of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical era- ...

Page 34

External Code Memory Access Memory Interface External Bus Cycles A/T89C51CC01 34 The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (PSEN#, and ALE). Figure 18 shows the structure ...

Page 35

Figure 19. External Code Fetch Waveforms CPU Clock ALE PSEN# P0 D7:0 P2 PCH Flash Memory Architecture Figure 20. Flash Memory Architecture Hardware Security (1 byte) Extra Row (128 Bytes) Column Latches (128 Bytes) 4129N–CAN–03/08 PCL D7:0 PCH T89C51CC01 features ...

Page 36

FM0 Memory Architecture User Space Extra Row (XRow) Hardware Security Byte Column Latches Cross Flash Memory Access Description A/T89C51CC01 36 The Flash memory is made blocks (see Figure 20): • The memory array (user space) 32K Bytes ...

Page 37

Overview of FM0 Operations Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column Launching Programming 4129N–CAN–03/08 The CPU interfaces to the Flash memory through the FCON register and AUXR1 ...

Page 38

Status of the Flash Memory Selecting FM1 Loading the Column Latches A/T89C51CC01 38 Table 26. Programming Spaces Write to FCON FPL3:0 FPS User Extra Row Hardware 5 X Security A X Byte ...

Page 39

Programming the Flash Spaces User Extra Row 4129N–CAN–03/08 Figure 21. Column Latches Loading Procedure Note: The last page address used when loading the column latch is the one used to select the page programming address. The following procedure is used ...

Page 40

Hardware Security Byte A/T89C51CC01 40 Figure 22. Flash and Extra Row Programming Procedure Column Latches Loading The following procedure is used to program the Hardware and is summarized in Figure 23: • Set FPS and map Hardware byte (FCON = ...

Page 41

Reading the Flash Spaces User Extra Row Hardware Security Byte 4129N–CAN–03/08 Figure 23. Hardware Programming Procedure Flash Spaces Programming Save and Disable FCON = 0Ch Data Load DPTR = 00h ACC = Data Exec: MOVX @DPTR, ...

Page 42

Flash Protection from Parallel Programming Preventing Flash Corruption A/T89C51CC01 42 Figure 24. Reading Procedure Flash Spaces Reading Flash Spaces Mapping FCON = 0000aa0b DPTR = Address Exec: MOVC A, @A+DPTR Note for the Hardware Security Byte. ...

Page 43

Registers 4129N–CAN–03/08 FCON RegisterFCON (S:D1h) Flash Control Register FPL3 FPL2 FPL1 Bit Bit Number Mnemonic Description Programming Launch Command Bits 7-4 FPL3:0 Write 5Xh followed by AXh to launch the programming according to FMOD1:0 (see Table 26) ...

Page 44

Operation Cross Memory Access Table 28. Cross Memory Access Action RAM Read boot FLASH Write Read FM0 Write External Read memory Write or Code Roll Over Note: 1. RWW: Read While Write A/T89C51CC01 44 Space addressable in ...

Page 45

Sharing Instructions 4129N–CAN–03/08 Table 29. Instructions shared XRAM EEPROM Action RAM ERAM Read MOV MOVX Write MOV MOVX Note: by cl: using Column Latch Table 30. Read MOVX A, @DPTR EEE bit in FPS in EECON Register FCON Register ENBOOT ...

Page 46

Table 32. Read MOVC A, @DPTR FCON Register Code Execution FMOD1 FMOD0 FPS From FM0 From FM1 (ENBOOT = External code EA=0 ...

Page 47

... This In-System-Programming (ISP) allows code modification over the total lifetime of the product. Besides the default Boot loader Atmel provide to the customer also all the needed Appli- cation-Programming-Interfaces (API) which are needed for the ISP. The API are located also in the Boot memory. ...

Page 48

... This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. - BLJB = 0 (i.e. bootloader FM1 executed after a reset) is the default Atmel factory pro- gramming read or modify this bit, the APIs are used. ...

Page 49

... Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made by functions. All of these APIs are described in detail in the following documents on the Atmel web site. • Datasheet Bootloader CAN T89C51CC01 • ...

Page 50

Hardware Security Byte A/T89C51CC01 50 Table 34. Hardware Security Byte X2B BLJB - Bit Bit Number Mnemonic Description X2 Bit 7 X2B Set this bit to start in standard mode. Clear this bit to start in X2 ...

Page 51

Serial I/O Port Figure 27. Serial I/O Port Block Diagram TXD RXD Framing Error Detection Figure 28. Framing Error Block Diagram 4129N–CAN–03/08 The T89C51CC01 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both ...

Page 52

Automatic Address Recognition A/T89C51CC01 52 Figure 29. UART Timing in Mode 1 RXD D0 D1 Start bit RI SMOD0=X FE SMOD0=1 Figure 30. UART Timing in Modes 2 and 3 RXD D0 D1 Start bit RI SMOD0=0 RI SMOD0=1 FE ...

Page 53

Given Address Broadcast Address 4129N–CAN–03/08 Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care ...

Page 54

Registers A/T89C51CC01 54 For slaves A and B, bit don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves ...

Page 55

Table 36. SADEN Register SADEN (S:B9h) Slave Address Mask Register – – – Bit Bit Number Mnemonic Description 7-0 Mask Data for Slave Individual Address Reset Value = 0000 0000b Not bit addressable Table 37. SADDR ...

Page 56

A/T89C51CC01 56 Table 39. PCON Register PCON (S:87h) Power Control Register SMOD1 SMOD0 – Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode ...

Page 57

Timers/Counters Timer/Counter Operations Timer 0 4129N–CAN–03/08 The T89C51CC01 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event ...

Page 58

Mode 0 (13-bit Timer) Figure 31. Timer/Counter Mode 0 See the “Clock” section FTx ÷ 6 CLOCK Tx C/Tx# TMOD reg INTx# GATEx TMOD reg Mode 1 (16-bit Timer) Figure 32. Timer/Counter x ...

Page 59

Mode 2 (8-bit Timer with Auto- Reload) Figure 33. Timer/Counter Mode 2 See the “Clock” section FTx ÷ 6 CLOCK Tx C/Tx# TMOD reg INTx# GATEx TMOD reg Mode 3 (Two 8-bit Timers) ...

Page 60

Timer 1 Mode 0 (13-bit Timer) Mode 1 (16-bit Timer) Mode 2 (8-bit Timer with Auto- Reload) Mode 3 (Halt) Interrupt A/T89C51CC01 60 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The ...

Page 61

Figure 35. Timer Interrupt System TF0 TCON.5 TF1 TCON.7 Timer 0 Interrupt Request ET0 IEN0.1 Timer 1 Interrupt Request ET1 IEN0.3 61 ...

Page 62

Registers A/T89C51CC01 62 Table 40. TCON Register TCON (S:88h) Timer/Counter Control Register TF1 TR1 TF0 Bit Bit Number Mnemonic Description Timer 1 Overflow Flag 7 TF1 Cleared by hardware when processor vectors to interrupt routine. Set by ...

Page 63

Table 41. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register GATE1 C/T1# M11 Bit Bit Number Mnemonic Description Timer 1 Gating Control Bit 7 GATE1 Clear to enable Timer 1 whenever TR1 bit is set. Set ...

Page 64

A/T89C51CC01 64 Table 42. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register – – – Bit Bit Number Mnemonic Description 7:0 High Byte of Timer 0. Reset Value = 0000 0000b Table 43. TL0 Register TL0 ...

Page 65

Table 45. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register – – – Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 1. Reset Value = 0000 0000b – – ...

Page 66

Timer 2 Auto-Reload Mode Figure 36. Auto-Reload Mode Up/Down Counter see section “Clock” FT2 CLOCK T2 A/T89C51CC01 66 The T89C51CC01 timer 2 is compatible with timer 2 in the 80C52 16-bit timer/counter: the count is maintained by ...

Page 67

Programmable Clock- Output Figure 37. Clock-Out Mode FT2 CLOCK T2 T2EX 4129N–CAN–03/08 In clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock genera- tor (See Figure 37). The input clock increments TL2 at frequency F repeatedly counts to overflow ...

Page 68

Registers A/T89C51CC01 68 Table 46. T2CON Register T2CON (S:C8h) Timer 2 Control Register TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. 7 TF2 ...

Page 69

Table 47. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...

Page 70

A/T89C51CC01 70 Table 49. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register Bit Bit Number Mnemonic Description 7-0 Low Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable Table 50. ...

Page 71

Watchdog Timer Figure 38. Watchdog Timer RESET Fwd Clock - 4129N–CAN–03/08 T89C51CC01 contains a powerful programmable hardware Watchdog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. ...

Page 72

Watchdog Programming A/T89C51CC01 72 The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 52. Machine Cycle Count ...

Page 73

Watchdog Timer During Power-down Mode and Idle Register 4129N–CAN–03/08 In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of exiting ...

Page 74

A/T89C51CC01 74 Table 55. WDTRST Register WDTRST (S:A6h Write only) Watchdog Timer Enable Register – – – Bit Bit Number Mnemonic Description 7 - Watchdog Control Value Reset Value = 1111 1111b Note: The WDRST register is ...

Page 75

CAN Controller CAN Protocol Principles Message Formats Can Standard Frame Figure 39. CAN Standard Frames Data Frame Bus Idle 11-bit identifier RTR IDE SOF SOF ID10..0 Interframe Arbitration Space Field Remote Frame Bus Idle 11-bit identifier RTR IDE SOF SOF ...

Page 76

CAN Extended Frame Figure 40. CAN Extended Frames Data Frame Bus Idle 11-bit base identifier SOF SOF SRR IDE IDT28..18 Interframe Arbitration Space Field Remote Frame Bus Idle 11-bit base identifier SRR IDE SOF SOF IDT28..18 Interframe Arbitration Space Field ...

Page 77

... It is the time required for the logic to determine the bit level of a sampled bit. The Information processing Time begins at the sample point, is measured in TQ and is fixed for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, Phase Segment 2 minimum shall not be less than the Information processing Time ...

Page 78

Bit Shortening Synchronization Jump Width Programming the Sample Point Arbitration Errors Error at Message Level A/T89C51CC01 78 If, on the other hand, the transmitter oscillator is faster than the receiver one, the next falling edge used for resynchronization may be ...

Page 79

Error at Bit Level Error Signalling CAN Controller Description 4129N–CAN–03/08 • ACK Errors As already mentioned frames received are acknowledged by all receivers through positive acknowledgement acknowledgement is received by the transmitter of the message an ACK error ...

Page 80

Figure 43. CAN Controller Block Diagram TxDC RxDC CAN Controller Mailbox and Registers Organization A/T89C51CC01 80 Bit Error Timing Counter Logic Rec/Tec Page DPR(Mailbox + Registers) Register µC-Core Interface Interface Core Bus Control The pagination allows management of the 321 ...

Page 81

Figure 44. CAN Controller Memory Organization SFR’s General Control General Status General Interrupt Bit Timing - 1 Bit Timing - 2 Bit Timing - 3 Enable message object - 1 Enable message object - 2 Enable Interrupt Enable Interrupt message ...

Page 82

Working on Message Objects CAN Controller Management A/T89C51CC01 82 The Page message object register (CANPAGE) is used to select one of the 15 message objects. Then, message object Control (CANCONCH) and message object Status (CANSTCH) are available for this selected ...

Page 83

Buffer Mode 4129N–CAN–03/08 Any message object can be used to define one buffer, including non-consecutive mes- sage objects, and with no limitation in number of message objects used up to 15. Each message object of the buffer must be initialized ...

Page 84

IT CAN Management Figure 46. CAN Controller Interrupt Structure CANGIE.5 ENRX RXOK i CANSTCH.5 TXOK i CANSTCH.6 BERR i CANSTCH.4 SERR i CANSTCH.3 CERR i CANSTCH.2 FERR i CANSTCH.1 AERR i CANSTCH.0 OVRBUF CANGIT.4 SERG CANGIT.3 CERG CANGIT.2 FERG CANGIT.1 ...

Page 85

Enable reception interrupt, ENRX. To enable an interrupt on message object error: • Enable General CAN IT in the interrupt system register, • Enable interrupt by message object, EICHi, • Enable interrupt on error, ENERCH. To enable an ...

Page 86

Bit Timing and Baud Rate Figure 47. Sample And Transmission Point FCAN Prescaler BRP CLOCK A/T89C51CC01 86 FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time quantum. So, the input clock for bit timing ...

Page 87

Figure 48. General Structure of a Bit Period oscillator system clock data (1) Phase error ≤ 0 (2) Phase error ≥ 0 (3) Phase error > 0 (4) Phase error < 0 4129N–CAN–03/08 1/ Fcan Bit Rate Prescaler Tscl one ...

Page 88

Fault Confinement A/T89C51CC01 88 With respect to fault confinement, a unit may be in one of the three following status: • error active • error passive • bus off An error active unit takes part in bus communication and can ...

Page 89

Acceptance Filter 4129N–CAN–03/08 Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received and an ID+RTR+RB+IDE specified while taking the comparison mask into account) the ID+RTR+RB+IDE received are written over the ID TAG Registers. ID => IDT0-29 RTR ...

Page 90

Data and Remote Frame message object in transmission message object disabled message object in transmission message object in by CAN controller reception message object disabled 1 message object in u transmission message object disabled 0 c message object in 0 ...

Page 91

Time Trigger Communication (TTC) and Message Stamping Figure 51. Block Diagram of CAN Timer Fcan ÷ 6 CLOCK TXOK i CANSTCH.4 RXOK i CANSTCH.5 CANSTMPH and CANSTMPL 4129N–CAN–03/08 The T89C51CC01 has a programmable 16-bit Timer (CANTIMH and CANTIML) for message ...

Page 92

CAN Autobaud and Listening Mode Routines Examples A/T89C51CC01 92 To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must be set. In this mode, the CAN controller is only listening to the line without acknowledg- ing the ...

Page 93

Enable the CAN macro CANGCON = 02h 2. Configure message object 3 in reception to receive only standard (11-bit identi- fier) message 100h // Select the message object 3 CANPAGE = 30h // Enable the interrupt on this ...

Page 94

A/T89C51CC01 94 4. Interrupt routine // Save the current CANPAGE // Find the first message object which generate an interrupt in CANSIT1 and CANSIT2 // Select the corresponding message object // Analyse the CANSTCH register to identify which kind of ...

Page 95

CAN SFR’s Table 57. CAN SFR’s With Reset Values (1) 0/8 1/9 IPL1 CH F8h xxxx x000 0000 0000 B F0h 0000 0000 IEN1 CL E8h xxxx x000 0000 0000 ACC E0h 0000 0000 CCON CMOD D8h 00x0 0000 00xx ...

Page 96

Registers A/T89C51CC01 96 Table 58. CANGCON Register CANGCON (S:ABh) CAN General Control Register ABRQ OVRQ TTC SYNCTTC Bit Number Bit Mnemonic Description Abort Request Not an auto-resetable bit. A reset of the ENCH bit (message object control ...

Page 97

Table 59. CANGSTA Register CANGSTA (S:AAh Read Only) CAN General Status Register OVFG - Bit Number Bit Mnemonic Description Reserved 7 - The values read from this bit is indeterminate. Do not set this bit. ...

Page 98

A/T89C51CC01 98 Table 60. CANGIT Register CANGIT (S:9Bh) CAN General Interrupt CANIT - OVRTIM Bit Number Bit Mnemonic Description General Interrupt Flag This status bit is the image of all the CAN controller interrupts sent to the ...

Page 99

Table 61. CANTEC Register CANTEC (S:9Ch Read Only) CAN Transmit Error Counter TEC7 TEC6 TEC5 Bit Number Bit Mnemonic Description Transmit Error Counter 7-0 TEC7:0 see Figure 49 Reset Value = 00h Table 62. CANREC Register ...

Page 100

A/T89C51CC01 100 Table 63. CANGIE Register CANGIE (S:C1h) CAN General Interrupt Enable ENRX Bit Number Bit Mnemonic Description Reserved 7-6 - The values read from these bits are indeterminate. Do not set these bits. Enable ...

Page 101

Table 65. CANEN2 Register CANEN2 (S:CFh Read Only) CAN Enable Message Object Registers ENCH7 ENCH6 ENCH5 Bit Number Bit Mnemonic Description Enable Message Object 0 - message object is disabled => the message object is ...

Page 102

A/T89C51CC01 102 Table 67. CANSIT2 Register CANSIT2 (S:BBh Read Only) CAN Status Interrupt Message Object Registers SIT7 SIT6 SIT5 Bit Number Bit Mnemonic Description Status of Interrupt by Message Object interrupt. 7-0 SIT7:0 ...

Page 103

Table 69. CANIE2 Register CANIE2 (S:C3h) CAN Enable Interrupt Message Object Registers IECH 7 IECH 6 IECH 5 Bit Number Bit Mnemonic Description Enable interrupt by Message Object 0 - disable IT. 7-0 IECH7:0 1 ...

Page 104

A/T89C51CC01 104 Table 71. CANBT2 Register CANBT2 (S:B5h) CAN Bit Timing Registers SJW 1 SJW 0 Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set ...

Page 105

Table 72. CANBT3 Register CANBT3 (S:B6h) CAN Bit Timing Registers PHS2 2 PHS2 1 Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this ...

Page 106

A/T89C51CC01 106 Table 73. CANPAGE Register CANPAGE (S:B1h) CAN Message Object Page Register CHNB 3 CHNB 2 CHNB 1 Bit Number Bit Mnemonic Description Selection of Message Object Number 7-4 CHNB3:0 The available numbers are ...

Page 107

Table 75. CANSTCH Register CANSTCH (S:B2h) CAN Message Object Status Register DLCW TXOK RXOK Bit Number Bit Mnemonic Description Data Length Code Warning The incoming message does not have the DLC expected. Whatever the frame 7 ...

Page 108

A/T89C51CC01 108 Table 76. CANIDT1 Register for V2.0 part A CANIDT1 for V2.0 part A (S:BCh) CAN Identifier Tag Registers IDT 10 IDT 9 IDT 8 Bit Number Bit Mnemonic Description IDentifier tag value 7-0 IDT10:3 ...

Page 109

Table 79. CANIDT4 Register for V2.0 part A CANIDT4 for V2.0 part A (S:BFh) CAN Identifier Tag Registers Bit Number Bit Mnemonic Description Reserved 7-3 - The values read from these bits ...

Page 110

A/T89C51CC01 110 Table 82. CANIDT3 Register for V2.0 part B CANIDT3 for V2.0 part B (S:BEh) CAN Identifier Tag Registers IDT 12 IDT 11 IDT 10 Bit Number Bit Mnemonic Description IDentifier Tag Value 7-0 IDT12:5 ...

Page 111

Table 85. CANIDM2 Register for V2.0 part A CANIDM2 for V2.0 part A (S:C5h) CAN Identifier Mask Registers IDMSK 2 IDMSK 1 IDMSK 0 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - comparison ...

Page 112

A/T89C51CC01 112 Table 87. CANIDM4 Register for V2.0 part A CANIDM4 for V2.0 part A (S:C7h) CAN Identifier Mask Registers Bit Number Bit Mnemonic Description Reserved 7-3 - The values read from these ...

Page 113

Table 89. CANIDM2 Register for V2.0 part B CANIDM2 for V2.0 part B (S:C5h) CAN Identifier Mask Registers IDMSK 20 IDMSK 19 IDMSK 18 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - comparison ...

Page 114

A/T89C51CC01 114 Table 91. CANIDM4 Register for V2.0 part B CANIDM4 for V2.0 part B (S:C7h) CAN Identifier Mask Registers IDMSK 4 IDMSK 3 IDMSK 2 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - ...

Page 115

Table 93. CANTCON Register CANTCON (S:A1h) CAN Timer ClockControl TPRESC 7 TPRESC 6 TPRESC 5 Bit Number Bit Mnemonic Description Timer Prescaler of CAN Timer This register is a prescaler for the main timer upper counter ...

Page 116

A/T89C51CC01 116 Table 96. CANSTMPH Register CANSTMPH (S:AFh Read Only) CAN Stamp Timer High TIMSTMP TIMSTMP TIMSTMP TIMSTMP Bit Number Bit Mnemonic Description High byte of Time Stamp 7-0 TIMSTMP15:8 See Figure 51. No ...

Page 117

Table 99. CANTTCL Register CANTTCL (S:A4h Read Only) CAN TTC Timer Low TIMTTC 7 TIMTTC 6 TIMTTC 5 Bit Number Bit Mnemonic Description Low byte of TTC Timer 7-0 TIMTTC7:0 See Figure 51. Reset Value = ...

Page 118

Programmable Counter Array (PCA) PCA Timer A/T89C51CC01 118 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which ...

Page 119

Figure 53. PCA Timer/Counter FPca/6 FPca/2 T0 OVF P1.2 Idle PCA Modules 4129N–CAN–03/08 CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 The CMOD register includes three additional bits associated with the PCA. • The CIDL bit which ...

Page 120

PCA Interrupt Figure 54. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 CMOD.0 PCA Capture Mode A/T89C51CC01 120 Each module in the PCA has a special function register associated with it (CCAPM0 for ...

Page 121

Figure 55. PCA Capture Mode CEXn 16-bit Software Timer Mode Figure 56. PCA 16-bit Software Timer and High Speed Output Mode PCA Counter CH (8 bits) (8 bits) “0” Reset Write to “1” CCAPnL Write to ...

Page 122

High Speed Output Mode Figure 57. PCA High Speed Output Mode Write to CCAPnH Reset Write to CCAPnL “0” “1” Enable Pulse Width Modulator Mode A/T89C51CC01 122 In this mode the CEX output (on port 1) associated with the PCA ...

Page 123

Figure 58. PCA PWM Mode CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CL (8 bits) PCA Watchdog Timer 4129N–CAN–03/08 CCAPnH CCAPnL 8-Bit Comparator ECOMn CCAPMn.6 CCAPMn.1 An on-board Watchdog timer is available with the PCA ...

Page 124

PCA Registers A/T89C51CC01 124 Table 100. CMOD Register CMOD (S:D9h) PCA Counter Mode Register CIDL WDTE - Bit Bit Number Mnemonic Description PCA Counter Idle Control bit 7 CIDL Clear to let the PCA run during Idle ...

Page 125

Table 101. CCON Register CCON (S:D8h) PCA Counter Control Register Bit Bit Number Mnemonic Description PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA 7 ...

Page 126

A/T89C51CC01 126 Table 102. CCAPnH Registers CCAP0H (S:FAh) CCAP1H (S:FBh) CCAP2H (S:FCh) CCAP3H (S:FDh) CCAP4H (S:FEh) PCA High Byte Compare/Capture Module n Register (n=0.. CCAPnH 7 CCAPnH 6 CCAPnH 5 CCAPnH 4 Bit Bit Number Mnemonic Description ...

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Table 104. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) PCA Compare/Capture Module n Mode registers (n=0.. ECOMn CAPPn Bit Bit Number Mnemonic Description Reserved 7 - The Value read from ...

Page 128

A/T89C51CC01 128 Table 105. CH Register CH (S:F9h) PCA Counter Register High Value Bit Bit Number Mnemonic Description 7:0 CH 7:0 High byte of Timer/Counter Reset Value = 0000 00000b Table ...

Page 129

Analog-to-Digital Converter (ADC) Features ADC Port 1 I/O Functions VAREF 4129N–CAN–03/08 This section describes the on-chip 10 bit analog-to-digital converter of the T89C51CC01. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer ...

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Figure 59. ADC Description ADC CLOCK AN0/P1.0 000 AN1/P1.1 001 AN2/P1.2 010 AN3/P1.3 011 AN4/P1.4 100 AN5/P1.5 101 AN6/P1.6 110 AN7/P1.7 111 SCH2 SCH1 ADCON.2 ADCON.1 Figure 60. Timing Diagram CLK ADEN (1) T SETUP ADSST ADEOC Notes: 1. Tsetup ...

Page 131

ADC Converter Operation Voltage Conversion Clock Selection 4129N–CAN–03/08 A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). After completion of the A/D conversion, the ADSST bit is cleared by hardware. The end-of-conversion flag ADEOC (ADCON.4) is ...

Page 132

Figure 61. A/D Converter clock CPU CLOCK CPU Core Clock Symbol ADC Standby Mode IT ADC Management Routines examples A/T89C51CC01 132 Prescaler ADCLK ÷ 2 When the ADC is not used possible to set it in standby mode ...

Page 133

SCH[2:0] ADCON and = F8h // Select the channel ADCON | = channel // Start conversion in precision mode ADCON | = 48h Note: to enable the ADC interrupt 133 ...

Page 134

Registers A/T89C51CC01 134 Table 108. ADCF Register ADCF (S:F6h) ADC Configuration Bit Bit Number Mnemonic Description Channel Configuration 7-0 CH 0:7 Set to use P1.x as ADC input. Clear to use ...

Page 135

Table 110. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler Bit Bit Number Mnemonic Description Reserved 7-5 - The value read from these bits are indeterminate. Do not set these bits. Clock Prescaler 4-0 ...

Page 136

Interrupt System Introduction Figure 63. Interrupt Control System External INT0# Interrupt 0 Timer 0 External INT1# Interrupt 1 Timer 1 CEX0:5 PCA TxD UART RxD Timer 2 TxDC CAN controller RxDC AIN1:0 Converter CAN Timer A/T89C51CC01 136 ...

Page 137

Each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all the ...

Page 138

Registers A/T89C51CC01 138 Table 115. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register ET2 Bit Bit Number Mnemonic Description Enable All Interrupt bit Clear to disable all interrupts Set to enable all interrupts. If ...

Page 139

Table 116. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - ...

Page 140

A/T89C51CC01 140 Table 117. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register PPC PT2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt ...

Page 141

Table 118. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...

Page 142

A/T89C51CC01 142 Table 119. IPH0 Register IPH0 (B7h) Interrupt High Priority Register PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA ...

Page 143

Table 120. IPH1 Register IPH1 (S:F7h) Interrupt High Priority Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...

Page 144

Electrical Characteristics Absolute Maximum Ratings Ambiant Temperature Under Bias industrial ....................................................... -40°C to 85°C Storage Temperature .................................... -65° 150°C Voltage on V from V ......................................-0. Voltage on Any Pin from V ...

Page 145

Notes: 1. Operating I is measured with all output pins disconnected; XTAL1 driven with (see Figure 67.), V CLCH CHCL 0.5V; XTAL2 N.C RST = Port ...

Page 146

A/T89C51CC01 146 Figure 65. I Test Condition, Idle Mode RST EA (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS Figure 66. I Test Condition, Power-Down Mode RST EA (NC) XTAL2 ...

Page 147

DC Parameters for A/D Converter Table 122. DC Parameters for AD Converter in Precision Conversion Symbol Parameter AVin Analog input voltage (2) Rref Resistance between Vref and Vss Varef Reference voltage Cai Analog input Capacitance Rai Analog input Resistor INL ...

Page 148

External Program Memory Characteristics A/T89C51CC01 148 Table 123. Symbol Description Symbol Parameter T Oscillator clock period T ALE pulse width LHLL T Address Valid to ALE AVLL T Address Hold After ALE LLAX T ALE to Valid Instruction In LLIV ...

Page 149

External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 4129N–CAN–03/08 Table 125. AC Parameters for a Variable Clock Symbol Type T Min LHLL T Min AVLL T Min LLAX T Max LLIV T ...

Page 150

External Data Memory Characteristics A/T89C51CC01 150 Table 126. Symbol Description Symbol Parameter T RD Pulse Width RLRH T WR Pulse Width WLWH Valid Data In RLDV T Data Hold After RD RHDX T Data Float After RD ...

Page 151

Table 128. AC Parameters for a Variable Clock Symbol Type T Min RLRH T Min WLWH T Max RLDV T Min RHDX T Max RHDZ T Max LLDV T Max AVDV T Min LLWL T Max LLWL T Min ...

Page 152

External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing – Shift Register Mode A/T89C51CC01 152 T ...

Page 153

Shift Register Timing Waveforms INSTRUCTION ALE CLOCK OUTPUT DATA WRITE to SBUF INPUT DATA External Clock Drive Characteristics (XTAL1) 4129N–CAN–03/08 Table 130. AC Parameters for a Fix Clock ( MHz) Symbol T XLXL T QVHX T XHQX T ...

Page 154

External Clock Drive Waveforms AC Testing Input/Output Waveforms Float Waveforms A/T89C51CC01 154 V -0.5V CC 0.7V CC 0.2V -0.1 0.45V CC T CHCL V -0.5V CC INPUT/OUTPUT 0.45V AC inputs during testing are driven at V Timing measurement are made ...

Page 155

Clock Waveforms STATE4 INTERNAL CLOCK P1 P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) READ CYCLE WRITE CYCLE PORT OPERATION MOV PORT SRC MOV DEST P0 MOV DEST ...

Page 156

Flash/EEPROM Memory A/D Converter A/T89C51CC01 156 Table 133. Timing Symbol Definitions Signals S (Hardware PSEN#,EA condition) R RST B FBUSY flag Table 134. Memory AC Timing VDD = 3V to 5.5V -40 to +85°C Symbol Parameter T Input ...

Page 157

... Ordering Information Table 136. Possible Order Entries Part Number Boot Loader T89C51CC01UA-7CTIM T89C51CC01UA-RLTIM T89C51CC01UA-SLSIM T89C51CC01CA-7CTIM T89C51CC01CA-RLTIM T89C51CC01CA-SLSIM AT89C51CC01UA-RLTUM UART AT89C51CC01UA-SLSUM UART AT89C51CC01CA-RLTUM CAN AT89C51CC01CA-SLSUM CAN 4129N–CAN–03/08 Temperature Range Package OBSOLETE Industrial & Green VQFP44 Industrial & Green PLCC44 Industrial & Green VQFP44 Industrial & ...

Page 158

Package Drawings VQFP44 A/T89C51CC01 158 4129N–CAN–03/08 ...

Page 159

STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP 1/ CONTROLLING DIMENSIONS : INCHES 2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M - 1982. 3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT ...

Page 160

PLCC44 A/T89C51CC01 160 4129N–CAN–03/08 ...

Page 161

STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm ...

Page 162

Datasheet Change Log for T89C51CC01 Changes from 4129F - 11/02 to 4129G - 04/03 Changes from 4129G - 04/03 to 4129H - 10/03 Changes from 4129H - 10/03 to 4129I - 12/03 Changes from 4129I - 12/03 to 4129J - ...

Page 163

Table of Contents Features ................................................................................................. 1 Description ............................................................................................ 2 Block Diagram ....................................................................................... 2 Pin Configuration .................................................................................. 3 SFR Mapping ......................................................................................... 8 Clock .................................................................................................... 14 Power Management ............................................................................ 18 Data Memory ....................................................................................... 23 EEPROM Data Memory ....................................................................... 30 I/O Configurations ................................................................................................ ...

Page 164

Program/Code Memory ...................................................................... 33 Operation Cross Memory Access ..................................................... 44 Sharing Instructions ........................................................................... 45 In-System Programming (ISP) ........................................................... 47 Serial I/O Port ...................................................................................... 51 Timers/Counters ................................................................................. 57 Timer 2 ................................................................................................. 66 Watchdog Timer .................................................................................. 71 CAN Controller .................................................................................... 75 ii ...

Page 165

CAN Controller Description ................................................................................ 79 CAN Controller Mailbox and Registers Organization ......................................... 80 CAN Controller Management ............................................................................. 82 IT CAN Management........................................................................................... 84 Bit Timing and Baud Rate .................................................................................. 86 Fault Confinement .............................................................................................. 88 Acceptance Filter................................................................................................ 89 Data and Remote Frame ...

Page 166

Ordering Information ........................................................................ 157 Package Drawings ............................................................................ 158 Datasheet Change Log for T89C51CC01 ........................................ 162 Table of Contents ................................................................................... i iv Absolute Maximum Ratings ............................................................................. 144 DC Parameters for Standard Voltage............................................................... 144 DC Parameters for A/D Converter.................................................................... 147 AC Parameters ...

Page 167

... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...

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