T89C51CC01CA-7CTIM Atmel, T89C51CC01CA-7CTIM Datasheet - Page 38

• Manufacturer Part Number: T89C51CC01CA-7CTIM
• Description: IC 8051 MCU FLASH 32K 64BGA
• Manufacturer: Atmel
• Series: AT89C CANr

Specifications of T89C51CC01CA-7CTIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• For Use With: AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: T89C51CC01CA7CTIM

Status of the Flash Memory
Selecting FM1
Loading the Column Latches
38
A/T89C51CC01
Table 26. Programming Spaces
Notes:
The bit FBUSY in FCON register is used to indicate the status of programming.
FBUSY is set when programming is in progress.
The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh.
Any number of data from 1 Byte to 128 Bytes can be loaded in the column latches. This
provides the capability to program the whole memory by byte, by page or by any number
of Bytes in a page.
When programming is launched, an automatic erase of the locations loaded in the col-
umn latches is first performed, then programming is effectively done. Thus no page or
block erase is needed and only the loaded data are programmed in the corresponding
page.
The following procedure is used to load the column latches and is summarized in
Figure 21:
•
•
•
•
•
•
Extra Row
Hardware
Reserved
Security
User
Byte
Save then disable interrupt and map the column latch space by setting FPS bit.
Load the DPTR with the address to load.
Load Accumulator register with the data to load.
Execute the MOVX @DPTR, A instruction.
If needed loop the three last instructions until the page is completely loaded.
Unmap the column latch and Restore Interrupt
1. The sequence 5xh and Axh must be executing without instructions between them
2. Interrupts that may occur during programming time must be disabled to avoid any
otherwise the programming is aborted.
spurious exit of the programming mode.
FPL3:0
A
A
A
A
5
5
5
5
FPS
Write to FCON
X
X
X
X
X
X
X
X
FMOD1
0
0
0
0
1
1
1
1
FMOD0
0
0
1
1
0
0
1
1
Operation
No action
Write the column latches in user
space
No action
Write the column latches in extra row
space
No action
Write the fuse bits space
No action
No action
4129N–CAN–03/08