T89C51CC01CA-7CTIM Atmel, T89C51CC01CA-7CTIM Datasheet - Page 107

• Manufacturer Part Number: T89C51CC01CA-7CTIM
• Description: IC 8051 MCU FLASH 32K 64BGA
• Manufacturer: Atmel
• Series: AT89C CANr

Specifications of T89C51CC01CA-7CTIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• For Use With: AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: T89C51CC01CA7CTIM

4129N–CAN–03/08
Table 75. CANSTCH Register
CANSTCH (S:B2h)
CAN Message Object Status Register
Note:
No default value after reset.
Number
DLCW
Bit
7
7
6
5
4
3
2
1
0
See Figure 46.
Bit Mnemonic Description
TXOK
DLCW
RXOK
BERR
SERR
CERR
AERR
TXOK
FERR
6
RXOK
Data Length Code Warning
The incoming message does not have the DLC expected. Whatever the frame
type, the DLC field of the CANCONCH register is updated by the received
DLC.
Transmit OK
The communication enabled by transmission is completed.
When the controller is ready to send a frame, if two or more message objects
are enabled as producers, the lower index message object (0 to 13) is
supplied first.
This flag can generate an interrupt and it must be cleared by software.
Receive OK
The communication enabled by reception is completed.
In the case of two or more message object reception hits, the lower index
message object (0 to 13) is updated first.
This flag can generate an interrupt and it must be cleared by software.
Bit Error (Only in Transmission)
The bit value monitored is different from the bit value sent.
Exceptions:
the monitored recessive bit sent as a dominant bit during the arbitration field
and the acknowledge slot detecting a dominant bit during the sending of an
error frame.
This flag can generate an interrupt and it must be cleared by software.
Stuff Error
Detection of more than five consecutive bits with the same polarity.
This flag can generate an interrupt and it must be cleared by software.
CRC Error
The receiver performs a CRC check on each destuffed received message
from the start of frame up to the data field.
If this checking does not match with the destuffed CRC field, a CRC error is
set.
This flag can generate an interrupt and it must be cleared by software.
Form Error
The form error results from one or more violations of the fixed form in the
following bit fields:
CRC delimiter
acknowledgment delimiter
end_of_frame
This flag can generate an interrupt.
Acknowledgment Error
No detection of the dominant bit in the acknowledge slot.
This flag can generate an interrupt and it must be cleared by software.
5
BERR
4
SERR
3
CERR
2
FERR
1
AERR
0
107