PIC18F25J10-I/SS Microchip Technology, PIC18F25J10-I/SS Datasheet - Page 59

• Manufacturer Part Number: PIC18F25J10-I/SS
• Description: IC PIC MCU FLASH 16KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F25J10-I/SS

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 21
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPIC, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180011 - MODULE PLUG-IN 18F25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164331 - MODULE SKT FOR 28SSOP 18F45J10XLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.3.4
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
the top half of Bank 15 (F80h to FFFh). A list of these
registers is given in Table 5-2 and Table 5-3.
TABLE 5-2:
© 2008 Microchip Technology Inc.
Note 1:
Address
FEDh POSTDEC0
FECh
FFDh
FFCh
FEEh POSTINC0
FEBh
FEAh
FFFh
FFEh
FFBh
FFAh
FEFh
FE9h
FE8h
FE7h
FE6h POSTINC1
FE5h POSTDEC1
FE4h
FE3h
FE2h
FE1h
FE0h
2:
3:
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
This is not a physical register.
Unimplemented registers are read as ‘0’.
This register is not available in 28-pin devices.
SPECIAL FUNCTION REGISTERS
PREINC0
PREINC1
PLUSW0
PLUSW1
TBLPTRU
TBLPTRH
TBLPTRL
INTCON2
INTCON3
STKPTR
PCLATU
PCLATH
INTCON
INDF0
INDF1
TABLAT
PRODH
PRODL
FSR0H
FSR1H
FSR0L
WREG
FSR1L
SPECIAL FUNCTION REGISTER MAP FOR PIC18F45J10 FAMILY DEVICES
TOSU
TOSH
Name
TOSL
BSR
PCL
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Address
FDDh POSTDEC2
FDCh
FCDh
FCCh
FDEh POSTINC2
FDBh
FDAh
FCEh
FCBh
FCAh
FDFh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
PREINC2
SSP1CON1
SSP1CON2
PLUSW2
SSP1STAT
SSP1ADD
WDTCON
SSP1BUF
OSCCON
ADRESH
ADCON0
ADCON1
ADCON2
ADRESL
INDF2
STATUS
TMR0H
T0CON
TMR1H
T1CON
T2CON
FSR2H
TMR0L
TMR1L
FSR2L
RCON
Name
TMR2
—
—
PR2
(2)
(2)
(1)
(1)
(1)
(1)
(1)
Address
PIC18F45J10 FAMILY
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the periph-
eral functions. The Reset and Interrupt registers are
described in their respective chapters, while the ALU’s
STATUS register is described later in this section.
Registers related to the operation of a peripheral feature
are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
FBEh
FBDh
FBCh
FBBh
FBAh
FACh
FBFh
FAEh
FADh
FABh
FAAh
FB9h
FB8h
FB7h ECCP1DEL
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
ECCP1AS
BAUDCON
EECON2
CCP1CON
CCP2CON
CVRCON
SPBRGH
CCPR1H
CCPR2H
EECON1
CCPR1L
CCPR2L
CMCON
SPBRG
RCREG
TXREG
RCSTA
TXSTA
Name
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
—
—
—
—
—
—
—
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(3)
(3)
Address
F9Dh
F9Ch
F8Dh
F8Ch
F9Eh
F9Bh
F9Ah
F8Eh
F8Bh
F8Ah
F9Fh
F99h
F98h
F97h
F96h
F94h
F93h
F92h
F91h
F8Fh
F89h
F88h
F87h SSP2STAT
F86h SSP2CON1
F85h SSP2CON2
F84h
F83h
F82h
F81h
F80h
F95h
F90h
DS39682D-page 57
SSP2ADD
SSP2BUF
PORTE
PORTD
TRISE
TRISD
PORTC
LATE
LATD
PORTB
PORTA
TRISC
TRISB
TRISA
Name
LATC
LATB
LATA
IPR1
PIR1
PIE1
—
—
—
—
—
—
—
—
—
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)