PIC18F25J10-I/SS Microchip Technology, PIC18F25J10-I/SS Datasheet - Page 221

• Manufacturer Part Number: PIC18F25J10-I/SS
• Description: IC PIC MCU FLASH 16KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F25J10-I/SS

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 21
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPIC, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180011 - MODULE PLUG-IN 18F25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164331 - MODULE SKT FOR 28SSOP 18F45J10XLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17.7
The A/D converter in the PIC18F45J10 family of
devices includes a self-calibration feature which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON0<7>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for offset. Thus, subsequent offsets will
be compensated.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
17.8
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
TABLE 17-2:
© 2008 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTB
TRISB
LATB
PORTE
TRISE
LATE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Name
(1)
(1)
(1)
A/D Converter Calibration
Operation in Power-Managed
Modes
These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
PORTB Data Direction Control Register
PORTB Data Latch Register (Read and Write to Data Latch)
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register High Byte
A/D Result Register Low Byte
PSPIF
PSPIE
PSPIP
OSCFIF
OSCFIE
OSCFIP
ADCAL
ADFM
Bit 7
RB7
IBF
—
—
—
—
—
REGISTERS ASSOCIATED WITH A/D OPERATION
(1)
(1)
(1)
CMIE
CMIP
ADIE
ADIP
CMIF
ADIF
Bit 6
RB6
OBF
—
—
—
—
—
—
—
TRISA5
VCFG1
ACQT2
CHS3
RCIE
RCIP
IBOV
RCIF
Bit 5
RA5
RB5
—
—
—
—
—
PSPMODE
VCFG0
ACQT1
INT0IE
CHS2
TXIE
TXIP
Bit 4
TXIF
RB4
—
—
—
—
—
—
—
PIC18F45J10 FAMILY
SSP1IE
SSP1IP
TRISA3
SSP1IF
BCL1IF
BCL1IE
BCL1IP
PCFG3
ACQT0
CHS1
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been com-
pleted. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in the Sleep mode requires the A/D RC clock
to be selected. If bits ACQT2:ACQT0 are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry to Sleep mode. The IDLEN
and SCS bits in the OSCCON register must have
already been cleared prior to starting the conversion.
RBIE
Bit 3
RA3
RB3
—
—
—
PORTE Data Latch Register
(Read and Write to Data Latch)
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISA2
TRISE2
PCFG2
ADCS2
CHS0
Bit 2
RA2
RB2
RE2
—
—
—
GO/DONE
TMR2IE
TMR2IP
TMR2IF
TRISA1
TRISE1
PCFG1
ADCS1
INT0IF
Bit 1
RA1
RB1
RE1
—
—
—
TMR1IE
TMR1IP
TMR1IF
CCP2IF
CCP2IE
CCP2IP
TRISA0
TRISE0
PCFG0
ADCS0
ADON
DS39682D-page 219
Bit 0
RBIF
RA0
RB0
RE0
on page
Values
Reset
43
45
45
45
45
45
45
44
44
44
44
44
46
46
46
46
46
46
46
46