PIC18F25J10-I/SS Microchip Technology, PIC18F25J10-I/SS Datasheet - Page 106

• Manufacturer Part Number: PIC18F25J10-I/SS
• Description: IC PIC MCU FLASH 16KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F25J10-I/SS

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 21
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPIC, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180011 - MODULE PLUG-IN 18F25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164331 - MODULE SKT FOR 28SSOP 18F45J10XLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F45J10 FAMILY
TABLE 9-9:
DS39682D-page 104
RD0/PSP0/SCK2/
SCL2
RD1/PSP1/SDI2/
SDA2
RD2/PSP2/SDO2
RD3/PSP3/SS2
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
Legend:
Pin
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
PORTD I/O SUMMARY
Function
SDO2
PSP0
SCK2
PSP1
SDA2
PSP2
PSP3
PSP4
PSP5
PSP6
PSP7
SCL2
SDI2
RD0
RD1
RD2
RD3
SS2
RD4
RD5
P1B
RD6
P1C
RD7
P1D
Setting
TRIS
0
1
x
x
0
1
0
1
0
1
x
x
1
1
1
0
1
x
x
0
0
1
x
x
1
0
1
x
x
0
1
x
x
0
0
1
x
x
0
0
1
x
x
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
2
C/SMB I
C/SMB I
Type
DIG
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
LATD<0> data output.
PORTD<0> data input.
PSP read data output (LATD<0>); takes priority over port data.
PSP write data input.
SPI clock output (MSSP2 module); takes priority over port data.
SPI clock input (MSSP2 module).
I
LATD<1> data output.
PORTD<1> data input.
PSP read data output (LATD<1>); takes priority over port data.
PSP write data input.
SPI data input (MSSP2 module).
I
LATD<2> data output.
PORTD<2> data input.
PSP read data output (LATD<2>); takes priority over port data.
PSP write data input.
SPI data output (MSSP2 module); takes priority over port data.
LATD<3> data output.
PORTD<3> data input.
PSP read data output (LATD<3>); takes priority over port data.
PSP write data input.
Slave select input for MSSP2 (MSSP2 module).
LATD<4> data output.
PORTD<4> data input.
PSP read data output (LATD<4>); takes priority over port data.
PSP write data input.
LATD<5> data output.
PORTD<5> data input.
PSP read data output (LATD<5>); takes priority over port data.
PSP write data input.
ECCP1 Enhanced PWM output, channel B; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
LATD<6> data output.
PORTD<6> data input.
PSP read data output (LATD<6>); takes priority over port data.
PSP write data input.
ECCP1 Enhanced PWM output, channel C; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
LATD<7> data output.
PORTD<7> data input.
PSP read data output (LATD<7>); takes priority over port data.
PSP write data input.
ECCP1 Enhanced PWM output, channel D; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
2
2
2
2
C™ clock output (MSSP2 module); takes priority over port data.
C clock input (MSSP2 module); input type depends on module setting.
C data output (MSSP2 module); takes priority over port data.
C data input (MSSP2 module); input type depends on module setting.
Description
I
2
C™/SMB = I
© 2008 Microchip Technology Inc.
2
C/SMBus input buffer;