PIC18F25J10-I/SS Microchip Technology, PIC18F25J10-I/SS Datasheet - Page 220

• Manufacturer Part Number: PIC18F25J10-I/SS
• Description: IC PIC MCU FLASH 16KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F25J10-I/SS

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 21
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPIC, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180011 - MODULE PLUG-IN 18F25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164331 - MODULE SKT FOR 28SSOP 18F45J10XLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

conversion sample. This means the ADRESH:ADRESL
PIC18F45J10 FAMILY
17.5
Figure 17-3 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 17-4 shows the operation of the A/D converter
after
ACQT2:ACQT0 bits are set to ‘010’ and selecting a
4 T
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
started. After this wait, acquisition on the selected
channel is automatically started.
FIGURE 17-3:
FIGURE 17-4:
DS39682D-page 218
Note:
(Holding capacitor continues
acquiring input)
AD
AD
Set GO/DONE bit
wait is required before the next acquisition can be
1
acquisition time before the conversion starts.
the
A/D Conversions
T
T
Set GO/DONE bit
CY
Automatic
Acquisition
Time
ACQT
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Holding capacitor is disconnected from analog input (typically 100 ns)
2
GO/DONE
- T
AD
Cycles
Conversion starts
T
3
AD
A/D CONVERSION T
A/D CONVERSION T
1 T
bit
4
AD
b9
2 T
Conversion starts
(Holding capacitor is disconnected)
has
1
AD
b8
3 T
been
b9
2
AD
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
b7
Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared,
4 T
set,
b8
3
AD
AD
AD
b6
5 T
CYCLES (ACQT2:ACQT0 = 000, T
CYCLES (ACQT2:ACQT0 = 010, T
ADIF bit is set, holding capacitor is reconnected to analog input.
the
ADIF bit is set, holding capacitor is connected to analog input.
b7
4
AD
b5
6 T
T
5
b6
AD
AD
b4
7 T
Cycles
17.6
An A/D conversion can be started by the “Special Event
Trigger” of the ECCP2 module. This requires that the
CCP2M3:CCP2M0
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to auto-
matically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
T
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
ACQ
b5
6
AD
b3
time is selected before the Special Event Trigger
8
Use of the ECCP2 Trigger
b4
T
7
AD
b2
9 T
b3
8
AD
b1
10
bits
T
b2
9
AD
© 2008 Microchip Technology Inc.
b0
11
ACQ
ACQ
10
(CCP2CON<3:0>)
b1
= 0)
= 4 T
b0
11
AD
)
be