PIC18F25J10-I/SS Microchip Technology, PIC18F25J10-I/SS Datasheet - Page 162

• Manufacturer Part Number: PIC18F25J10-I/SS
• Description: IC PIC MCU FLASH 16KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F25J10-I/SS

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 21
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPIC, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180011 - MODULE PLUG-IN 18F25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164331 - MODULE SKT FOR 28SSOP 18F45J10XLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F45J10 FAMILY
15.4.2
The MSSP module functions are enabled by setting the
MSSP Enable bit, SSPEN (SSPxCON1<5>).
The SSPxCON1 register allows control of the I
operation.
(SSPxCON1<3:0>) allow one of the following I
modes to be selected:
• I
• I
• I
• I
• I
• I
Selection of any I
forces the SCLx and SDAx pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCLx and SDAx pins.
15.4.3
In Slave mode, the SCLx and SDAx pins must be
configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
The I
interrupt on an exact address match. In addition,
address masking will also allow the hardware to gener-
ate an interrupt for more than one address (up to 31 in
7-bit addressing and up to 63 in 10-bit addressing).
Through the mode select bits, the user can also choose
to interrupt on Start and Stop bits.
When an address is matched, or the data transfer after
an address match is received, the hardware auto-
matically will generate the Acknowledge (ACK) pulse
and load the SSPxBUF register with the received value
currently in the SSPxSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF (SSPxSTAT<0>), was set
• The MSSP Overflow bit, SSPOV
In this case, the SSPxSR register value is not loaded
into the SSPxBUF, but the SSPxIF bit is set. The BF bit
is cleared by reading the SSPxBUF register, while the
SSPOV bit is cleared through software.
DS39682D-page 160
clock = (F
Stop bit interrupts enabled
Stop bit interrupts enabled
slave is Idle
before the transfer was received.
(SSPxCON1<6>), was set before the transfer was
received.
2
2
2
2
2
2
C Master mode,
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address) with Start and
C Slave mode (10-bit address) with Start and
C Firmware Controlled Master mode,
2
C Slave mode hardware will always generate an
OPERATION
SLAVE MODE
OSC
Four
/4) x (SSPxADD + 1)
2
C mode, with the SSPEN bit set,
mode
selection
bits
2
2
C
C
The SCLx clock input must have a minimum high and
low for proper operation. The high and low times of the
I
MSSP module, are shown in timing parameter 100 and
parameter 101.
15.4.3.1
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPxSR register. All
incoming bits are sampled with the rising edge of the
clock (SCLx) line. The value of register SSPxSR<7:1>
is compared to the value of the SSPxADD register. The
address is compared on the falling edge of the eighth
clock (SCLx) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1.
2.
3.
4.
In 10-Bit Addressing mode, two address bytes need to
be received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPxSTAT<2>) must specify a write
so the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘11110
A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the
address. The sequence of events for 10-Bit Addressing
mode is as follows, with steps 7 through 9 for the
slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
2
C specification, as well as the requirement of the
The SSPxSR register value is loaded into the
SSPxBUF register.
The Buffer Full bit, BF, is set.
An ACK pulse is generated.
The MSSP Interrupt Flag bit, SSPxIF, is set (and
interrupt is generated, if enabled) on the falling
edge of the ninth SCLx pulse.
Receive first (high) byte of address (bits,
SSPxIF, BF and UA (SSPxSTAT<1>), are set).
Update the SSPxADD register with second (low)
byte of address (clears bit, UA, and releases the
SCLx line).
Read the SSPxBUF register (clears bit, BF) and
clear flag bit, SSPxIF.
Receive second (low) byte of address (bits,
SSPxIF, BF and UA, are set).
Update the SSPxADD register with the first
(high) byte of address. If match releases SCLx
line, this will clear bit, UA.
Read the SSPxBUF register (clears bit, BF) and
clear flag bit, SSPxIF.
Receive Repeated Start condition.
Receive first (high) byte of address (bits,
SSPxIF and BF, are set).
Read the SSPxBUF register (clears bit, BF) and
clear flag bit, SSPxIF.
Addressing
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