PIC18F25J10-I/SS Microchip Technology, PIC18F25J10-I/SS Datasheet - Page 356

• Manufacturer Part Number: PIC18F25J10-I/SS
• Description: IC PIC MCU FLASH 16KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F25J10-I/SS

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 21
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPIC, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180011 - MODULE PLUG-IN 18F25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164331 - MODULE SKT FOR 28SSOP 18F45J10XLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F45J10 FAMILY
Timer0 .............................................................................. 111
Timer1 .............................................................................. 115
Timer2 .............................................................................. 121
Timing Diagrams
DS39682D-page 354
Associated Registers ............................................... 113
Clock Source Select (T0CS Bit) ............................... 112
Operation ................................................................. 112
Overflow Interrupt .................................................... 113
Prescaler .................................................................. 113
Prescaler Assignment (PSA Bit) .............................. 113
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 113
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 112
Source Edge Select (T0SE Bit) ................................ 112
Switching Prescaler Assignment .............................. 113
16-Bit Read/Write Mode ........................................... 117
Associated Registers ............................................... 120
Interrupt .................................................................... 118
Operation ................................................................. 116
Oscillator .......................................................... 115, 117
Oscillator, as Secondary Clock .................................. 26
Overflow Interrupt .................................................... 115
Resetting, Using the ECCP/CCP
Special Event Trigger (ECCP) ................................. 132
TMR1H Register ...................................................... 115
TMR1L Register ....................................................... 115
Use as a Clock Source ............................................ 118
Use as a Real-Time Clock ....................................... 119
Associated Registers ............................................... 122
Interrupt .................................................................... 122
Operation ................................................................. 121
Output ...................................................................... 122
PR2 Register .................................................... 128, 133
TMR2-to-PR2 Match Interrupt .......................... 128, 133
A/D Conversion ........................................................ 330
Acknowledge Sequence .......................................... 181
Asynchronous Reception ......................................... 202
Asynchronous Transmission .................................... 200
Asynchronous Transmission (Back to Back) ........... 200
Automatic Baud Rate Calculation ............................ 198
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 203
Baud Rate Generator with Clock Arbitration ............ 175
BRG Overflow Sequence ......................................... 198
BRG Reset Due to SDAx Arbitration During
Brown-out Reset (BOR) ........................................... 318
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start
Bus Collision During a Stop
Bus Collision During a Stop
Bus Collision During Start
Bus Collision for Transmit and Acknowledge ........... 183
Capture/Compare/PWM (Including
Layout Considerations ..................................... 118
Special Event Trigger ....................................... 119
Normal Operation ............................................. 203
Start Condition ................................................. 185
Condition (Case 1) ........................................... 186
Condition (Case 2) ........................................... 186
Condition (SCLx = 0) ....................................... 185
Condition (Case 1) ........................................... 187
Condition (Case 2) ........................................... 187
Condition (SDAx Only) ..................................... 184
ECCP Module) ................................................. 320
CLKO and I/O .......................................................... 317
Clock Synchronization ............................................. 168
Clock/Instruction Cycle .............................................. 52
EUSART Synchronous Receive (Master/Slave) ...... 329
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 321
Example SPI Master Mode (CKE = 1) ..................... 322
Example SPI Slave Mode (CKE = 0) ....................... 323
Example SPI Slave Mode (CKE = 1) ....................... 324
External Clock (All Modes Except PLL) ................... 315
Fail-Safe Clock Monitor ........................................... 242
First Start Bit Timing ................................................ 176
Full-Bridge PWM Output .......................................... 137
Half-Bridge PWM Output ......................................... 136
I
I
I
I
I
I
I
I
I
I
I
I
Master SSP I
Master SSP I
Parallel Slave Port (PSP) Read ............................... 110
Parallel Slave Port (PSP) Write ............................... 110
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 139
PWM Direction Change at Near
PWM Output ............................................................ 128
Repeated Start Condition ........................................ 177
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 204
Slave Synchronization ............................................. 151
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 150
SPI Mode (Slave Mode, CKE = 0) ........................... 152
SPI Mode (Slave Mode, CKE = 1) ........................... 152
Synchronous Reception (Master Mode, SREN) ...... 207
Synchronous Transmission ..................................... 205
Synchronous Transmission (Through TXEN) .......... 206
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up (MCLR
Timer0 and Timer1 External Clock .......................... 319
Transition for Entry to Idle Mode ................................ 35
Transition for Entry to SEC_RUN Mode .................... 32
Transition for Entry to Sleep Mode ............................ 34
Transition for Two-Speed Start-up (INTRC) ............ 240
Transition for Wake From Idle to Run Mode .............. 35
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 325
C Bus Start/Stop Bits ............................................ 325
C Master Mode (7 or 10-Bit Transmission) ........... 179
C Master Mode (7-Bit Reception) .......................... 180
C Slave Mode (10-Bit Reception, SEN = 0) .......... 165
C Slave Mode (10-Bit Reception, SEN = 1) .......... 170
C Slave Mode (10-Bit Transmission) .................... 166
C Slave Mode (7-Bit Reception, SEN = 0) ............ 163
C Slave Mode (7-Bit Reception, SEN = 1) ............ 169
C Slave Mode (7-Bit Transmission) ...................... 164
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ........ 182
(Master/Slave) ................................................. 329
Sequence (7 or 10-Bit Address Mode) ............ 171
Auto-Restart Disabled) .................................... 142
Auto-Restart Enabled) ..................................... 142
100% Duty Cycle ............................................. 139
Timer (OST) and Power-up Timer (PWRT) ..... 318
V
(MCLR Not Tied to V
(MCLR Not Tied to V
Tied to V
DD
Rise < T
2
2
DD
C Bus Data ........................................ 327
C Bus Start/Stop Bits ........................ 327
, V
PWRT
DD
© 2008 Microchip Technology Inc.
Rise > T
) ............................................ 41
DD
DD
), Case 1 ...................... 41
), Case 2 ...................... 41
PWRT
DD
,
) ....................... 40