PIC18F25J10-I/SS Microchip Technology, PIC18F25J10-I/SS Datasheet - Page 351

• Manufacturer Part Number: PIC18F25J10-I/SS
• Description: IC PIC MCU FLASH 16KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F25J10-I/SS

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 21
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPIC, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180011 - MODULE PLUG-IN 18F25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164331 - MODULE SKT FOR 28SSOP 18F45J10XLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Electrical Characteristics .................................................. 299
Enhanced Capture/Compare/PWM (ECCP) .................... 131
Enhanced PWM Mode. See PWM (ECCP Module). ........ 133
Enhanced Universal Synchronous Asynchronous
Equations
Errata ................................................................................... 6
EUSART
Extended Instruction Set
External Clock Input (EC Modes) ....................................... 24
F
Fail-Safe Clock Monitor ............................................ 231, 241
Fast Register Stack ............................................................ 51
© 2008 Microchip Technology Inc.
Associated Registers ............................................... 144
Capture and Compare Modes .................................. 132
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration ....................................... 132
Pin Configurations for ECCP1 Modes ...................... 132
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 132
Timer Resources ...................................................... 132
Receiver Transmitter (EUSART). See EUSART.
A/D Acquisition Time ................................................ 216
A/D Minimum Charging Time ................................... 216
Asynchronous Mode ................................................ 199
Baud Rate Generator
Baud Rate Generator (BRG) .................................... 193
Synchronous Master Mode ...................................... 205
Synchronous Slave Mode ........................................ 208
ADDFSR .................................................................. 288
ADDULNK ................................................................ 288
and Using MPLAB IDE Tools ................................... 294
CALLW ..................................................................... 289
Considerations for Use ............................................ 292
MOVSF .................................................................... 289
MOVSS .................................................................... 290
PUSHL ..................................................................... 290
SUBFSR .................................................................. 291
SUBULNK ................................................................ 291
Syntax ...................................................................... 287
Interrupts in Power-Managed Modes ....................... 242
POR or Wake-up from Sleep ................................... 242
WDT During Oscillator Failure ................................. 241
12-Bit Break Transmit and Receive ................. 204
Associated Registers, Receive ........................ 202
Associated Registers, Transmit ....................... 200
Auto-Wake-up on Sync Break ......................... 202
Receiver ........................................................... 201
Setting Up 9-Bit Mode with
Transmitter ....................................................... 199
Operation in Power-Managed Mode ................ 193
Associated Registers ....................................... 194
Auto-Baud Rate Detect .................................... 197
Baud Rate Error, Calculating ........................... 194
Baud Rates, Asynchronous Modes ................. 195
High Baud Rate Select (BRGH Bit) ................. 193
Sampling .......................................................... 193
Associated Registers, Receive ........................ 207
Associated Registers, Transmit ....................... 206
Reception ......................................................... 207
Transmission ................................................... 205
Associated Registers, Receive ........................ 209
Associated Registers, Transmit ....................... 208
Reception ......................................................... 209
Transmission ................................................... 208
Address Detect ........................................ 201
PIC18F45J10 FAMILY
Firmware Instructions ...................................................... 245
Flash Configuration Words .............................................. 231
Flash Program Memory ..................................................... 67
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 266
H
Hardware Multiplier ............................................................ 77
I
I/O Ports ............................................................................ 93
I
2
C Mode (MSSP)
Associated Registers ................................................. 75
Control Registers ....................................................... 68
Erase Sequence ........................................................ 72
Erasing ...................................................................... 72
Operation During Code-Protect ................................. 75
Reading ..................................................................... 71
Table Pointer
Table Pointer Boundaries .......................................... 70
Table Reads and Table Writes .................................. 67
Write Sequence ......................................................... 73
Writing To .................................................................. 73
Introduction ................................................................ 77
Operation ................................................................... 77
Performance Comparison .......................................... 77
Acknowledge Sequence Timing .............................. 181
Associated Registers ............................................... 188
Baud Rate Generator .............................................. 174
Bus Collision
Clock Arbitration ...................................................... 175
Clock Stretching ...................................................... 167
Clock Synchronization and the CKP Bit .................. 168
Effects of a Reset .................................................... 182
General Call Address Support ................................. 171
I
Master Mode ............................................................ 172
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 182
Operation ................................................................. 160
Read/Write Bit Information (R/W Bit) ............... 160, 162
Registers ................................................................. 155
Serial Clock (SCKx/SCLx) ....................................... 162
2
C Clock Rate w/BRG ............................................ 174
EECON1 and EECON2 ..................................... 68
TABLAT (Table Latch) ....................................... 70
TBLPTR (Table Pointer) .................................... 70
Boundaries Based on Operation ....................... 70
Protection Against Spurious Writes ................... 75
Unexpected Termination ................................... 75
Write Verify ........................................................ 75
During a Repeated Start Condition .................. 186
During a Stop Condition .................................. 187
10-Bit Slave Receive Mode (SEN = 1) ............ 167
10-Bit Slave Transmit Mode ............................ 167
7-Bit Slave Receive Mode (SEN = 1) .............. 167
7-Bit Slave Transmit Mode .............................. 167
Baud Rate Generator ...................................... 174
Operation ......................................................... 173
Reception ........................................................ 178
Repeated Start Condition Timing .................... 177
Start Condition Timing ..................................... 176
Transmission ................................................... 178
and Arbitration ................................................. 182
DS39682D-page 349