C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 45

• Manufacturer Part Number: C8051F930DK
• Description: KIT DEV C8051F920,F921,F930,F931
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930DK

• Contents: Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F920, F921, F930, F931
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1473

Table 4.2. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Digital Supply Current—Suspend and Sleep Mode
Digital Supply Current
(Suspend Mode)
Digital Supply Current
(Sleep Mode, SmaRTClock
running)
Digital Supply Current
(Sleep Mode)
Notes:
1. Based on device characterization data; Not production tested.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained with
4. Includes oscillator and regulator supply current.
5. IDD can be estimated for frequencies <10 MHz by simply multiplying the frequency of interest by the frequency
6. The supply current specifications in Table 4.2 are for two cell mode. The VBAT current in one-cell mode can be
7. Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the
the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration requires 3
CPU clock cycles, and the Flash memory is read on each cycle. The supply current will vary slightly based on the
physical location of the sjmp instruction and the number of Flash address lines that toggle as a result. In the worst
case, current can increase by up to 30% if the sjmp loop straddles a 128-byte Flash address boundary (e.g.,
0x007F to 0x0080). Real-world code with larger loops and longer linear sequences will have few transitions across
the 128-byte address boundaries.
sensitivity number for that range, then adding an offset of 90 µA. When using these numbers to estimate I
>10 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency
sensitivity number. For example: V
estimated using the following equation:
The VBAT Voltage is the voltage at the VBAT pin, typically 0.9 to 1.8 V.
The Supply Current (two-cell mode) is the data sheet specification for supply current.
The Supply Voltage is the voltage at the VDD/DC+ pin, typically 1.8 to 3.3 V (default = 1.9 V).
The DC-DC Converter Efficiency can be estimated using Figure 4.3–Figure 4.5.
frequency sensitivity number. For example: V
20 MHz) x 0.120 mA/MHz = 3.5 mA.
5 MHz) x 0.095 mA/MHz = 0.6 mA.
Parameter
VBAT Current (one-cell mode)
6

V
1.8 V, T = 25
3.0 V, T = 25
3.6 V, T = 25
1.8 V, T = 85
3.0 V, T = 85
3.6 V, T = 85
(includes SmaRTClock oscillator and VBAT
Supply Monitor)
1.8 V, T = 25 °C
3.0 V, T = 25 °C
3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
(includes VBAT supply monitor)
DD
= 1.8–3.6 V, two-cell mode
DD
= 3.0 V; F = 20 MHz, I
=
°
°
°
°
°
°
C
C
C
C
C
C
DD
---------------------------------------------------------------------------------------------------------------------------------- -
Supply Voltage Supply Current (two-cell mode)
Conditions
DC-DC Converter Efficiency VBAT Voltage
= 3.0 V; F = 5 MHz, Idle I
Rev. 1.1
C8051F93x-C8051F92x
DD

= 4.1 mA – (25 MHz –
DD

= 2.5 mA – (25 MHz –
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
0.60
0.75
0.85
1.30
1.60
1.90
0.05
0.08
0.12
0.75
0.90
1.20
Typ
77
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
DD
Units
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
for
45