C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 198

KIT DEV C8051F920,F921,F930,F931

C8051F930DK

Manufacturer Part Number
C8051F930DK
Description
KIT DEV C8051F920,F921,F930,F931
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F930DK

Contents
Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F920, F921, F930, F931
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1473

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F930DK
Manufacturer:
Silicon Labs
Quantity:
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C8051F93x-C8051F92x
20.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers
The SmaRTClock internal registers can be read and written using RTC0ADR and RTC0DAT. The
RTC0ADR register selects the SmaRTClock internal register that will be targeted by subsequent reads or
writes. Recommended instruction timing is provided in this section. If the recommended instruction timing
is not followed, then BUSY (RTC0ADR.7) should be checked prior to each read or write operation to make
sure the SmaRTClock Interface is not busy performing the previous read or write operation. A
SmaRTClock Write operation is initiated by writing to the RTC0DAT register. Below is an example of
writing to a SmaRTClock internal register.
A SmaRTClock Read operation is initiated by setting the SmaRTClock Interface Busy bit. This transfers
the contents of the internal register selected by RTC0ADR to RTC0DAT. The transferred data will remain in
RTC0DAT until the next read or write operation. Below is an example of reading a SmaRTClock internal
register.
Note: The RTC0ADR and RTC0DAT registers will retain their state upon a device reset.
20.1.3. RTC0ADR Short Strobe Feature
Reads and writes to indirect SmaRTClock registers normally take 7 system clock cycles. To minimize the
indirect register access time, the Short Strobe feature decreases the read and write access time to 6
system clocks. The Short Strobe feature is automatically enabled on reset and can be manually
enabled/disabled using the SHORT (RTC0ADR.4) control bit.
Recommended Instruction Timing for a single register read with short strobe enabled:
mov RTC0ADR, #095h
nop
nop
nop
mov A, RTC0DAT
Recommended Instruction Timing for a single register write with short strobe enabled:
mov RTC0ADR, #095h
mov RTC0DAT, #000h
nop
198
1. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommended instruction timing.
2. Write 0x05 to RTC0ADR. This selects the internal RTC0CN register at SmaRTClock Address
3. Write 0x00 to RTC0DAT. This operation writes 0x00 to the internal RTC0CN register.
1. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommended instruction timing.
2. Write 0x05 to RTC0ADR. This selects the internal RTC0CN register at SmaRTClock Address
3. Write 1 to BUSY. This initiates the transfer of data from RTC0CN to RTC0DAT.
4. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommend instruction timing.
5. Read data from RTC0DAT. This data is a copy of the RTC0CN register. 
0x05.
0x05.
Rev. 1.1

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