C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 271

• Manufacturer Part Number: C8051F930DK
• Description: KIT DEV C8051F920,F921,F930,F931
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930DK

• Contents: Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F920, F921, F930, F931
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1473

SFR Definition 24.1. SPInCFG: SPI Configuration
SFR Addresses: SPI0CFG = 0xA1, SPI1CFG = 0x84 
SFR Pages: SPI0CFG = 0x0, SPI1CFG = 0x0
*Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 24.1 for timing parameters.
SPIBSY
SLVSEL
MSTEN
RXBMT
CKPHA
CKPOL
SPIBSY
NSSIN
Name
SRMT
R
7
0
MSTEN
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
SPI Clock Phase.
0: Data centered on first edge of SCK period.
1: Data centered on second edge of SCK period.
SPI Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
Slave Selected Flag.
Set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It
is cleared to logic 0 when NSS is high (slave not selected). This bit does not indi-
cate the instantaneous value at the NSS pin, but rather a de-glitched version of the
pin input.
NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
Shift Register Empty (valid in slave mode only).
Set to logic 1 when data has been transferred in/out of the shift register, and there
is no data is available to read from the transmit buffer or write to the receive buffer.
Set to logic 0 when a data byte is transferred to the shift register from the transmit
buffer or by a transition on SCK. Note: SRMT = 1 in Master Mode.
Receive Buffer Empty (valid in slave mode only).
Set to logic 1 when the receive buffer has been read and contains no new informa-
tion. If there is new information available in the receive buffer that has not been
read, this bit will return to logic 0. Note: RXBMT = 1 in Master Mode.
R/W
0
6
CKPHA
R/W
5
0
CKPOL
R/W
Rev. 1.1
4
0
C8051F93x-C8051F92x
SLVSEL
Function
R
3
0
*
NSSIN
*
R
2
1
SRMT
R
1
1
RXBMT
R
0
1
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