C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 115

• Manufacturer Part Number: C8051F930DK
• Description: KIT DEV C8051F920,F921,F930,F931
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930DK

• Contents: Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F920, F921, F930, F931
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1473

10.4. Multiplexed External Memory Interface
For a Multiplexed external memory interface, the Data Bus and the lower 8-bits of the Address Bus share
the same Port pins: AD[7:0]. For most devices with an 8-bit interface, the upper address bits are not used
and can be used as GPIO if the external memory interface is used in 8-bit non-banked mode. If the
external memory interface is used in 8-bit banked mode, or 16-bit mode, then the address pins will be
driven with the upper 4 address bits and cannot be used as GPIO.
Many devices with a slave parallel memory interface, such as SRAM chips, only support a non-multiplexed
memory bus. When interfacing to such a device, an external latch (74HC373 or equivalent logic gate) can
be used to hold the lower 8-bits of the RAM address during the second half of the memory cycle when the
address/data bus contains data. The external latch, controlled by the ALE (Address Latch Enable) signal,
is automatically driven by the External Memory Interface logic. An example SRAM interface showing
multiplexed to non-multiplexed conversion is shown in Figure 10.2.
This example is showing that the external MOVX operation can be broken into two phases delineated by
the state of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are
presented to AD[7:0]. During this phase, the address latch is configured such that the Q outputs reflect the
states of the D inputs. When ALE falls, signaling the beginning of the second phase, the address latch
outputs remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the Data
Bus controls the state of the AD[7:0] port at the time RD or WR is asserted.
See Section “10.6. External Memory Interface Timing” on page 118 for detailed timing diagrams.
I
E
F
M
AD[7:0]
A[11:8]
Figure 10.1. Multiplexed Configuration Example
ALE
WR
RD
ADDRESS BUS (12-bit or 8-bit)
DATA BUS
Rev. 1.1
GPIO (4-bit)
(Optional)
C8051F93x-C8051F92x
V
DD
8
CS
RD
WR
ALE
AD[7:0]
(8-bit Interface)
LEDs/Switches
Controller
Ethernet
115