C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 42

KIT DEV C8051F920,F921,F930,F931

C8051F930DK

Manufacturer Part Number
C8051F930DK
Description
KIT DEV C8051F920,F921,F930,F931
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F930DK

Contents
Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F920, F921, F930, F931
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1473

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F930DK
Manufacturer:
Silicon Labs
Quantity:
135
C8051F93x-C8051F92x
42
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
the solder mask and the metal pad is to be 60 µm minimum, all the way around
the pad.
should be used to assure good solder paste release.
specification for Small Body Components.
Dimension
Figure 3.9. Typical LQFP-32 Landing Diagram
C1
C2
X1
Y1
E
Table 3.7. PCB Land Pattern
Rev. 1.1
8.40
8.40
0.40
1.25
MIN
0.80 BSC
MAX
8.50
8.50
0.50
1.35

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