C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 289

• Manufacturer Part Number: C8051F930DK
• Description: KIT DEV C8051F920,F921,F930,F931
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930DK

• Contents: Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F920, F921, F930, F931
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1473

25.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 25.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8 or
Comparator 0 output. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bits (T2XCLK[1:0] in TMR2CN), as follows:
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is
generated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check
the TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt
flags are not cleared by hardware and must be manually cleared by software.
T2MH
0
0
0
0
1
SmaRTClock / 8
Comparator 0
SYSCLK / 12
T2XCLK[1:0]
00
01
10
11
X
T2XCLK[1:0]
00
01
11
Figure 25.5. Timer 2 8-Bit Mode Block Diagram
SYSCLK / 12
SmaRTClock / 8
Reserved
Comparator 0
SYSCLK
SYSCLK
TMR2H Clock
Source
0
1
1
0
M
H
T
3
M
T
3
L
CKCON
M
T
2
H
M
T
2
L
M
T
1
M
T
0
TR2
S
C
A
1
C
S
A
0
Rev. 1.1
TCLK
TCLK
C8051F93x-C8051F92x
TMR2RLH
TMR2RLL
T2ML
TMR2H
TMR2L
0
0
0
0
1
Reload
Reload
T2XCLK[1:0]
00
01
10
11
X
To SMBus
To ADC,
TF2CEN
T2SPLIT
SMBus
TF2LEN
T2XCLK
TF2H
TF2L
TR2
SYSCLK / 12
SmaRTClock / 8
Reserved
Comparator 0
SYSCLK
TMR2L Clock
Source
Interrupt
289