mc68hc908kx8 Freescale Semiconductor, Inc, mc68hc908kx8 Datasheet - Page 89

• Manufacturer Part Number: mc68hc908kx8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

7.7.3 ICG Trim Register
TRIM7:TRIM0 — ICG Trim Factor Bits
7.7.4 ICG DCO Divider Register
DDIV3:DDIV0 — ICG DCO Divider Control Bits
7.7.5 ICG DCO Stage Register
Freescale Semiconductor
These read/write bits change the size of the internal capacitor used by the internal clock generator. By
testing the frequency of the internal clock and incrementing or decrementing this factor accordingly,
the accuracy of the internal clock can be improved to ±2%. Incrementing this register by one decreases
the frequency by 0.195% of the unadjusted value. Decrementing this register by one increases the
frequency by 0.195%. This register cannot be written when the CMON bit is set. Reset sets these bits
to $80, centering the range of possible adjustment.
These bits indicate the number of divide-by-twos (DDIV) that follow the digitally controlled oscillator.
When ICGON is set, DDIV is controlled by the digital loop filter. The range of valid values for DDIV is
from $0 to $9. Values of $A–$F are interpreted the same as $9. Since the DCO is active during reset,
reset has no effect on DSTG and the value may vary.
Address: $0038
Address: $0039
Address: $003A
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
DSTG7
TRIM7
Bit 7
Bit 7
Bit 7
Figure 7-14. ICG DCO Divider Control Register (ICGDVR)
Figure 7-15. ICG DCO Stage Control Register (ICGDSR)
R
U
1
0
= Unimplemented
= Unimplemented
= Unimplemented
DSTG6
TRIM6
Figure 7-13. ICG Trim Register (ICGTR)
R
U
6
0
6
0
6
DSTG5
TRIM5
5
R
U
5
0
5
0
DSTG4
TRIM4
4
R
U
R
4
0
4
0
U = Undefined
= Reserved
DSTG3
TRIM3
DDIV3
U
3
R
U
3
0
3
DSTG2
TRIM2
DDIV2
U = Unaffected
U
2
R
U
2
0
2
DSTG1
TRIM1
DDIV1
U
1
R
U
1
0
1
DSTG0
TRIM0
DDIV0
Bit 0
Bit 0
Bit 0
U
R
U
0
I/O Registers
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