mc68hc908kx8 Freescale Semiconductor, Inc, mc68hc908kx8 Datasheet - Page 71

• Manufacturer Part Number: mc68hc908kx8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

reference with comparators, whose outputs are fed to the digital loop filter. The dependence of these
outputs on the capacitor size, current reference, and voltage reference causes up to ±25% error in f
7.3.2.4 Digital Loop Filter
The digital loop filter (DLF) uses the outputs of the frequency comparator to adjust the internal clock
(ICLK) clock period. The DLF generates the DCO divider control bits (DDIV[3:0]) and the DCO stage
control bits (DSTG[7:0]), which are fed to the DCO. The DLF first concatenates the DDIV and DSTG
registers (DDIV[3:0]:DSTG[7:0]) and then adds or subtracts a value dependent on the relative error in the
low frequency base clock’s period, as shown in
operating at a V
maximum ($9FF) or below the minimum ($000). In both cases, the value for DDIV will be between $A and
$F. In this range, the DDIV value will be interpreted the same as $9 (the slowest condition). Recovering
from this condition requires subtracting (increasing frequency) in the normal fashion until the value is
again below $9FF (if the desired value is $9xx, the value may settle at $Axx through $Fxx — this is an
acceptable operating condition). If the error is less than ±15%, the ICG’s filter stable indicator (FICGS) is
set, indicating relative frequency accuracy to the clock monitor.
All FLASH mask sets other than 0K45D, 1K45D, 0L09H, 1L09H have 15% comparators that improve
stability at low temperatures.
7.3.3 External Clock Generator
The ICG also provides for an external oscillator or external clock source, if desired. The external clock
generator, shown in
7.3.3.1 External Oscillator Amplifier
The external oscillator amplifier provides the gain required by an external crystal connected in a Pierce
oscillator configuration. The amount of this gain is controlled by the slow external (EXTSLOW) bit in the
CONFIG (or MOR) register. When EXTSLOW is set, the amplifier gain is reduced for operating
low-frequency crystals (32 kHz to 100 kHz). When EXTSLOW is clear, the amplifier gain will be sufficient
for 1 MHz to 8 MHz crystals. EXTSLOW must be configured correctly for the given crystal or the circuit
may not operate.
Freescale Semiconductor
1. x =Maximum error is independent of value in DDIV[3:0]. DDIV increments or decrements when an addition to DSTG[7:0]
of IBASE compared
IBASE < 0.85 f
0.85 f
IBASE < 1.15 f
1.15 f
carries or borrows.
Frequency Error
IBASE < f
f
NOM
to f
NOM
NOM
< IBASE
NOM
< IBASE
< IBASE
NOM
NOM
NOM
DD
level which is out of specification, the DLF may attempt to use a value above the
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Figure
DDVI[3:0]:DSTG[7:0]
7-3, contains an external oscillator amplifier and an external clock input path.
Table 7-1. Correction Sizes from DLF to DCO
+32 (+$020)
–32 (–$020)
Correction
+1 (+$001)
–1 (–$001)
Table
Maximum
Maximum
Maximum
Maximum
Minimum
Minimum
Minimum
Minimum
DDIV[3:0]:DSTG[7:0]
Current to New
7-1. In some extreme error conditions, such as
$xFF to $xDF
$xDF to $xFF
$xFF to $xFE
$xFE to $xFF
$x20 to $x00
$x01 to $x00
$x00 to $x01
$x00 to $x20
(1)
–0.0625/17.0625
+0.0625/30.9375
–0.0625/31
+0.0625/17
Relative Correction
–2/31
+2/29
+2/17
–2/19
Functional Description
in DCO
–0.202%
–0.366%
+0.202%
+0.368%
–6.45%
–10.5%
+6.90%
+11.8%
NOM
71
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