mc68hc908kx8 Freescale Semiconductor, Inc, mc68hc908kx8 Datasheet - Page 74

• Manufacturer Part Number: mc68hc908kx8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Internal Clock Generator Module (ICG)
near 307.2 kHz. For proper operation, EREF must be at least twice as slow as IBASE and IREF must be
at least twice as slow as ECLK.
To guarantee that IREF is slower than ECLK and EREF is slower than IBASE, one of the signals is divided
down. Which signal is divided and by how much is determined by the external slow (EXTSLOW) and
external crystal enable (EXTXTALEN) bits in the CONFIG (or MOR) register, according to the rules in
Table
To conserve size, the long divider (divide by 4096) is also used as an external crystal stabilization divider.
The divider is reset when the external clock generator is turned off or in STOP (ECGEN is clear). When
the external clock generator is first turned on, the external clock generator stable bit (ECGS) will be clear.
This condition automatically selects ECLK as the input to the long divider. The external stabilization clock
(ESTBCLK) will be ECLK divided by 16 when EXTXTALEN is low or 4096 when EXTXTALEN is high.
This time-out allows the crystal to stabilize. The falling edge of ESTBCLK is used to set ECGS (ECGS will
set after a full 16 or 4096 cycles). When ECGS is set, the divider returns to its normal function. ESTBCLK
may be generated by either IBASE or ECLK, but any clocking will only reinforce the set condition. If ECGS
is cleared because the clock monitor determined that ECLK was inactive, the divider will revert to a
stabilization divider. Since this will change the EREF and IREF divide ratios, it is important to turn the
clock monitor off (CMON = 0) after inactivity is detected to ensure valid recovery.
74
0
1
1
1
1
1
1
x
1. U = Unaffected; refer to section of table where ICGON or ECGON is set to 1.
2. IBASE is always used as the internal frequency (307.2 kHz).
x
0
1
1
1
1
1
1
7-2.
0
0
0
1
1
1
1
x
0
0
1
1
x
x
x
x
Each signal (IBASE and ECLK) is always divided by four. A longer divider
is used on either IBASE or ECLK based on the EXTSLOW bit.
x
x
0
1
0
1
0
1
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Maximum
Maximum
Maximum
Maximum
Maximum
Maximum
Minimum
Minimum
Minimum
Minimum
Minimum
Minimum
Frequency
Table 7-2. Clock Monitor Reference Divider Ratios
External
U
0
307.2 kHz
307.2 kHz
100 kHz
32 MHz
32 MHz
30 kHz
30 kHz
8 MHz
1 MHz
8 MHz
60 Hz
60 Hz
Divider
EREF
Ratio
128*4
128*4
1*4
1*4
Off
Off
Off
U
NOTE
Frequency
1.953 kHz
15.63 kHz
62.5 kHz
76.8 kHz
25.0 kHz
7.5 kHz
600 Hz
EREF
15 Hz
U
0
0
0
ESTBCLK
(IBASE)
(IBASE)
Divider
(ECLK)
(ECLK)
(ECLK)
(ECLK)
Ratio
4096
4096
4096
Off
16
16
16
U
(2)
(2)
Frequency
ESTBCLK
7.324 kHz
1.953 kHz
1.953 kHz
19.2 kHz
19.2 kHz
2.0 MHz
2.0 MHz
3.75 Hz
244 Hz
± 25%
± 25%
75 Hz
U
0
Freescale Semiconductor
Divider
Ratio
4096*4
IREF
16*4
1*4
1*4
1*4
1*4
Off
U
(1)
Frequency
18.75 Hz
76.8 kHz
76.8 kHz
76.8 kHz
76.8 kHz
± 125%
4.8 kHz
± 25%
± 25%
± 25%
± 25%
± 25%
IREF
U
0