mc68hc908kx8 Freescale Semiconductor, Inc, mc68hc908kx8 Datasheet - Page 139

• Manufacturer Part Number: mc68hc908kx8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

13.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in
originates from either an external oscillator or from the internal clock generator.
13.2.1 Bus Timing
In user mode, the internal bus frequency is the internal clock generator output (CGMXCLK) divided by
four.
13.2.2 Clock Startup from POR or LVI Reset
When the power-on reset (POR) module or the low-voltage inhibit (LVI) module generates a reset, the
clocks to the CPU and peripherals are inactive and held in an inactive phase until after 4096 CGMXCLK
cycles. The MCU is held in reset by the SIM during this entire period. The bus clocks start upon completion
of the timeout.
13.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows CGMXCLK to clock the SIM counter.
The CPU and peripheral clocks do not become active until after the stop delay timeout. Stop mode
recovery timing is discussed in detail in
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
Freescale Semiconductor
GENERATOR
ICG
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
ECLK
ICLK
SELECT
CIRCUIT
CLOCK
CS
ICG
MONITOR MODE
Figure 13-3. System Clock Signals
USER MODE
13.6.2 Stop
÷
2
A
B S*
Mode.
*WHEN S = 1,
CGMOUT = B
CGMXCLK
CGMOUT
SIM Bus Clock Control and Generation
÷
SIM COUNTER
2
SIM
Figure
GENERATORS
BUS CLOCK
13-3. This clock
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