mc68hc908kx8 Freescale Semiconductor, Inc, mc68hc908kx8 Datasheet - Page 142

• Manufacturer Part Number: mc68hc908kx8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
If the stop enable bit, STOP, in the configuration register (CONFIG1) is 0, the SIM treats the STOP
instruction as an illegal opcode and causes an illegal opcode reset.
13.3.1.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset.
13.3.1.5 Forced Monitor Mode Entry Reset (MENRST)
The MENRST module is monitoring the reset vector fetches and will assert an internal reset if it detects
that the reset vectors are erased ($FF). When the MCU comes out of reset, it is forced into monitor mode.
See
16.3 Monitor ROM
(MON).
13.3.1.6 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the V
voltage falls to the V
DD
TRIPF
voltage. The LVI bit in the SIM reset status register (SRSR) is set and a chip reset is asserted if the
LVIPWRD and LVIRSTD bits in the CONFIG register are at 0. The MCU is held in reset until V
rises
DD
above V
The MCU remains in reset until the SIM counts 4096 CGMXCLK to begin a reset recovery.
TRIPR.
Another 64 CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to
occur. See
Chapter 10 Low-Voltage Inhibit
(LVI).
13.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the
clock for the COP module. The SIM counter is 12 bits long and is clocked by the falling edge of
CGMXCLK.
13.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the internal clock generator to drive the
bus clock state machine.
13.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the configuration
register. If the SSREC bit is a 1, then the stop recovery is reduced from the normal delay of 4096
CGMXCLK cycles down to 32 CGMXCLK cycles.
13.4.3 SIM Counter and Reset States
The SIM counter is free-running after all reset states. See
13.3.1 Active Resets from Internal Sources
for
counter control and internal reset recovery sequences.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
142
Freescale Semiconductor