mc68hc908kx8 Freescale Semiconductor, Inc, mc68hc908kx8 Datasheet - Page 47

• Manufacturer Part Number: mc68hc908kx8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 4
Configuration Register (CONFIG)
4.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers
control these options:
4.2 Functional Description
The configuration registers are used in the initialization of various options and can be written once after
each reset. All of the configuration register bits are cleared during reset. Since the various options affect
the operation of the microcontroller unit (MCU), it is recommended that these registers be written
immediately after reset. The configuration registers are located at $001E and $001F. For compatibility, a
write to a read-only memory (ROM) version of the MCU at this location will have no effect. The
configuration register may be read at anytime.
Freescale Semiconductor
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Stop mode recovery time, 32 CGMXCLK cycles or 4096 CGMXCLK cycles
Computer operating properly (COP) timeout period, 2
STOP instruction
Computer operating properly (COP) module
Low-voltage inhibit (LVI) module control and voltage trip point selection
Enable/disable the oscillator (OSC) during stop mode
Serial communications interface (SCI) clock source selection
External clock/crystal source control
Enable/disable for the FLASH charge-pump regulator
Address:
Reset:
Read:
Write:
The CONFIG module is known as an MOR (mask option register) on a
ROM device. On a ROM device, the options are fixed at the time of device
fabrication and are neither writable nor changeable by the user.
On a FLASH device, the CONFIG registers are special registers containing
one-time writable latches after each reset. Upon a reset, the CONFIG
registers default to predetermined settings as shown in
Figure
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
$001E
Bit 7
4-2.
R
0
Figure 4-1. Configuration Register 2 (CONFIG2)
= Unimplemented
6
0
0
XTALEN
EXT-
5
0
NOTE
SLOW
EXT-
R
4
0
= Reserved
CLKEN
EXT-
18
3
0
–2
4
or 2
13
2
0
0
Figure 4-1
–2
4
CGMXCLK cycles
OSCENIN-
STOP
1
0
and
SCIBD-
SRC
Bit 0
0
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