mc68hc908kx8 Freescale Semiconductor, Inc, mc68hc908kx8 Datasheet - Page 85

• Manufacturer Part Number: mc68hc908kx8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

7.6.3 Slow External Clock (EXTSLOW)
Slow external clock (EXTSLOW), when set, will decrease the drive strength of the oscillator amplifier,
enabling low-frequency crystal operation (30 kHz–100 kHz) if properly enabled with the external clock
enable (EXTCLKEN) and external crystal enable (EXTXTALEN) bits. When clear, EXTSLOW enables
high-frequency crystal operation (1 MHz to 8 MHz).
EXTSLOW, when set, also configures the clock monitor to expect an external clock source that is slower
than the low-frequency base clock (60 Hz–307.2 kHz). When EXTSLOW is clear, the clock monitor will
expect an external clock faster than the low-frequency base clock (307.2 kHz–32 MHz).
The default state for this option is clear.
7.6.4 Oscillator Enable In Stop (OSCENINSTOP)
Oscillator enable in stop (OSCENINSTOP), when set, will enable the ICG to continue to generate clocks
(either CGMXCLK, CGMOUT, or TBMCLK) in stop mode. This function is used to keep the timebase
running while the rest of the microcontroller stops. When OSCENINSTOP is clear, all clock generation
will cease and CGMXCLK, CGMOUT, and TBMCLK will be forced low during stop.
The default state for this option is clear.
7.7 I/O Registers
The ICG contains five registers, summarized in
Several of the bits in these registers have interaction where the state of one bit may force another bit to
a particular state or prevent another bit from being set or cleared. A summary of this interaction is shown
in
Freescale Semiconductor
$0035
$0037
$0038
Addr.
Table
•
•
•
•
•
ICG control register
ICG multiplier register
ICG trim register
ICG DCO divider control register
ICG DCO stage control register
ICG Multiplier Register
7-5.
Register Name
ICG Control Register
ICG Trim Register
See page 87.
See page 88.
See page 89.
(ICGMR)
(ICGCR)
(ICGTR)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Figure 7-10. ICG Module I/O Register Summary
1. See CMF bit description for method of clearing.
TRIM7
CMIE
Bit 7
0
0
1
= Unimplemented
TRIM6
CMF
0
N6
6
0
0
0
(1)
Figure
CMON
TRIM5
N5
0
0
0
5
7-10. These registers are:
TRIM4
CS
N4
R
4
0
1
0
= Reserved
ICGON
TRIM3
N3
3
1
0
0
TRIM2
ICGS
U = Unaffected
N2
2
0
1
0
ECGON
TRIM1
N1
1
0
0
0
I/O Registers
TRIM0
ECGS
Bit 0
N0
0
1
0
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