mc68hc908kx8 Freescale Semiconductor, Inc, mc68hc908kx8 Datasheet - Page 124

• Manufacturer Part Number: mc68hc908kx8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Communications Interface Module (SCI)
12.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
12.5.1 Wait Mode
The SCI module remains active in wait mode. Any enabled CPU interrupt request from the SCI module
can bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
12.5.2 Stop Mode
The SCI module is inactive in stop mode. The STOP instruction does not affect SCI register states. SCI
module operation resumes after the MCU exits stop mode.
Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission
or reception results in invalid data.
12.6 I/O Signals
Port B shares two of its pins with the SCI module. The two SCI I/O pins are:
12.6.1 TxD (Transmit Data)
The TxD pin is the serial data output from the SCI transmitter. The SCI shares the TxD pin with port B.
When the SCI is enabled, the TxD pin is an output regardless of the state of the DDRB5 bit in data
direction register B (DDRB).
12.6.2 RxD (Receive Data)
The RxD pin is the serial data input to the SCI receiver. The SCI shares the RxD pin with port B. When
the SCI is enabled, the RxD pin is an input regardless of the state of the DDRB4 bit in data direction
register B (DDRB).
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Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break
characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3
enables NF to generate SCI error CPU interrupt requests.
Framing error (FE) — The FE bit in SCS1 is set when a 0 occurs where the receiver expects a stop
bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU
interrupt requests.
Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data.
The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt
requests.
TxD — Transmit data
RxD — Receive data
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor