mc68hc908kx8 Freescale Semiconductor, Inc, mc68hc908kx8 Datasheet - Page 141

• Manufacturer Part Number: mc68hc908kx8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

13.3.1.1 Power-On Reset
When power is first applied to the MCU, the power-on reset (POR) module generates a pulse to indicate
that power-on has occurred. The MCU is held in reset while the SIM counter counts out 4096 CGMXCLK
cycles. Another 64 CGMXCLK cycles later, the CPU and memories are released from reset to allow the
reset vector sequence to occur.
At power-on, these events occur:
13.3.1.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the reset status register (SRSR).
To prevent a COP module timeout, write any value to location $FFFF. Writing to location $FFFF clears
the COP counter and stages 12–5 of the SIM counter. The SIM counter output, which occurs at least
every 2
possible out of reset to guarantee the maximum amount of time before the first timeout.
The COP module is disabled if the IRQ1 pin is held at V
module can be disabled only through combinational logic conditioned with the high-voltage signal on the
IRQ1 pin. This prevents the COP from becoming disabled as a result of external noise.
13.3.1.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
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A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables CGMOUT.
Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow
stabilization of the internal clock generator.
The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are
cleared.
CGMXCLK
12
CGMOUT
PORRST
–2
IRST
IAB
4
CGMXCLK cycles, drives the COP counter. The COP should be serviced as soon as
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
CYCLES
4096
Figure 13-6. POR Recovery
CYCLES
64
TST
while the MCU is in monitor mode. The COP
$FFFE
Reset and System Initialization
$FFFF
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