mc68hc908kx8 Freescale Semiconductor, Inc, mc68hc908kx8 Datasheet - Page 123

• Manufacturer Part Number: mc68hc908kx8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

12.4.3.6 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems,
the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the
receiver into a standby state during which receiver interrupts are disabled.
Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the
receiver out of the standby state:
12.4.3.7 Receiver Interrupts
These sources can generate CPU interrupt requests from the SCI receiver:
12.4.3.8 Error Interrupts
These receiver error flags in SCS1 can generate CPU interrupt requests:
Freescale Semiconductor
1. Address mark — An address mark is a 1 in the most significant bit position of a received character.
2. Idle input line condition — When the WAKE bit is clear, an idle character on the RxD pin wakes the
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
character with no errors is
•
•
•
When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing
the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can then
compare the character containing the address mark to the user-defined address of the receiver. If
they are the same, the receiver remains awake and processes the characters that follow. If they
are not the same, software can set the RWU bit and put the receiver back into the standby state.
receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver
does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type bit,
ILTY, determines whether the receiver begins counting 1s as idle character bits after the start bit
or after the stop bit.
SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has
transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting
the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver
CPU interrupts.
Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive 1s shifted in from the
RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate CPU
interrupt requests.
Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new
character before the previous character was read from the SCDR. The previous character remains
in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3
enables OR to generate SCI error CPU interrupt requests.
With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
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170
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100
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3.53%.
Functional Description
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