pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 97

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
7.5.1 External Video Improvement Post Processing
QVCP supports the semi-planar YUV formats for one layer. Both layers support only
indexed, RGB and packed YUV formats. QVCP does not support planar video
formats. See
The mixer stage combines images from back to front, also allowing mixing in of a
fixed backdrop color. The mixing operation can be controlled by chroma range keying.
Mixing modes include per-pixel alpha blending, and color inverting. Mixing operations
can be programmed by a set of raster operations (ROP). Mixing is performed either
entirely in the RGB domain or the YUV domain, depending on the output mode of
operation of the QVCP. After mixing, post-processing optionally down samples 4:4:4
to 4:2:2 in the Chroma Down Sampler (CDS). Then, VBI insertion may be performed
(656 mode only), and the output is formatted to one of the forms as described below:
In each of the output modes, optional H-sync, V-sync and blanking or odd/even
outputs are available.
The QVCP can be slaved to an external timing source that provides a pixel clock and
a frame sync, i.e. VSYNC. The horizontal sync reference is taken from the frame
sync. Synchronizing to a traditional field-based Vertical Sync is not supported. The
clock direction is programmed in the clock module while the VSYNC direction, pin
VDO_D[29] is programmed in the QVCP module.
PNX17xx Series contains a TFT LCD controller. It has integrated control of the
synchronization signals but also all the LCD specific commands like power
management. De-Interlacing of video material is provided in the MBS module.
Dithering is handled by the QVCP-GNSH block.
The QVCP has separate synthesizers for pixel-clock generation. Software may use
these synthesizers to achieve perfect lock to the transmission source of the digital
video that is being displayed by the QVCP.
QVCP shares its allocated pins with the FGPO module through an output router.
Refer to
allocation.
The PNX17xx Series has a ‘VDO_AUX’ output pin that can be set to signal whether a
pixel is a graphics or video pixel. This can be used to suppress post-processing on
graphics elements for an attached proprietary video improvement post processor.
Motion vectors computed by TM5250 software can be sent to a video improvement
post-processor over the PCI interface.
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Screen timing generation adopted to the connected display requirements (SD-
TV standards, HD-TV standards, progressive, interlaced formats, LCD panel
control)
24- or 30-bit full parallel RGB or YUV
16- or 20-bit Y and U/V multiplexed data
8- or 10-bit 656 (full D1, 4:2:2 YUV with embedded sync codes)
8- or 10-bit 4:4:4 format in 656-style with RGB or YUV
Section 9.
Table 5
Rev. 1 — 17 March 2006
for the different operating modes of QVCP and FGPO and pin
for more details.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 2: Overview
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