pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 574

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
4. Signal Descriptions
PNX17XX_SER_1
Preliminary data sheet
4.1.1 System Interface Requirements
4.1 External Interface Pins
The SPDIF Input module has a single input pin. The signal applied to this pin must
have TTL level voltage swing.
Table 5: SPDIF Input Pin Summary
For the commonly found 0.5 Vpp SPDIF signal (IEC60958 consumer mode), the user
must externally restore the signal to TTL voltage levels. In all cases, external isolation
of the input signal is recommended.
IEC60958 specifies that consumer systems have a 0.5 Vpp signal driven from the
transmitter into an unbalanced cable with a 75 ohm nominal impedance. The load
side must present a 75-ohm resistive impedance over the frequency band of
0.1 to 6 MHz.
The circuit presents a simple RS422 differential receiver. The chosen receiver should
have good input hysteresis. Also, the signal applied to the SPDIF Input input pin
should ideally have a 50% duty cycle. It is recommended that the system designer
add an isolation transformer to the input circuit. Other consumer input circuits may be
possible.
Signal
SPDI_IN
Figure 8:
•
•
SWS (Last subframe) - this event signal indicates that a single 32-bit subframe
corresponding to the last sample in the currently filling memory buffer has been
received at the input to SPDIF Input. The event is NOT qualified with a particular
block boundary. This represents a precise, periodic event for use by system
software to achieve audio/video synchronization.
All SPDI_STATUS register bits (except LOCK) - these events can be used by
software to either count or timestamp any interrupt generated by SPDIF Input.
Refer to
Phono
RCA
SPDIF Input Consumer interface
Table 6
Type
IN
Figure 8
Rev. 1 — 17 March 2006
differential voltage swing is 0.5Vpp
for details regarding SPDIF Input interrupt sources.
Description
Single-ended SPDIF Input pin. Input sample rate can be 32 kHz,
44.1 kHz, 48 kHz or 96 kHz. Input signal must be TTL compatible.
presents an input circuit that satisfies the load requirements.
75 ohm
0v
+v
-v
+
-
RS-422 receiver
with good input hysteresis
TTL output
need 50% duty cycle
Vdd
0v
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 18: SPDIF Input
SPDIF Input
18-14