pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 243

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 7: PCI-XIO Register Summary
PNX17XX_SER_1
Preliminary data sheet
Bit
0x0000—0x000C
0x04 0010
0x04 0014
0x04 0018
0x04 001C
0x04 0020
0x04 0024
0x04 0028
0x04 002C
0x04 0030
0x04 0034
0x04 0038
0x04 003C
0x04 0040
0x04 0044
0x04 0048
0x04 004C
0x04 0050
0x04 0054
0x04 0058
0x04 005C—0068
0x04 006C
0x04 0070
0x04 0074
0x04 0078
0x04 007C
0x04 0080
0x04 0084
0x04 0088
0x04 008C
0x04 0090
0x04 0094—07FC
0x04 0800
0x04 0804
0x04 0808
0x04 080C
5.1 Register Summary
Symbol
Reserved
pci_setup
pci_control
pci_base1_lo
pci_base1_hi
pci_base2_lo
pci_base2_hi
read_lifetime
gppm_addr
gppm_wdata
gppm_rdata
gppm_ctrl
unlock_register
device/vendorid
config_cmd_stat
class code/rev id
latency timer
base10
base14
base18
Reserved
subsystem ids
Reserved
cap_pointer
Reserved
config_misc
pmc
pwr_state
pci_io
slv_tuning
dma_tuning
Reserved
dma_eaddr
dma_iaddr
dma_length
dma_ctrl
Description
PCI Setup register
PCI Control register
Internal view of external PCI bottom address, 1st aperture
Internal view of external PCI top address, 1st aperture
Internal view of external PCI bottom address, 2nd aperture
Internal view of external PCI top address, 2nd aperture
Length of time data is held exclusively for requesting agent.
General purpose PCI Master Cycle address register
General purpose PCI Master Cycle write data register
General purpose PCI Master Cycle read data register
General purpose PCI Master Cycle control register
Unlock pci_setup, class code, subsystem_ids
Image of device id and vendor id (config reg 00)
Image of configuration command and status register (config reg 04)
Image of class code and revision id (config reg 08)
Image of latency timer, cache line size (config reg 0C)
Image of configuration base address10 (config reg 10)
Image of configuration base address14 (config reg 14)
Image of configuration base address18 (config reg 18)
Subsystem id, subsystem vendor id (config reg 2C)
Image of capabilities pointer (config reg 34)
Image of interrupt line, and interrupt line registers
(config reg 3C)
Power management capabilities (config reg 40)
Power Management control (config reg 44)
PCI IO properties
Slave DTL tuning
DMA DTL tuning
PCI address for DMA transaction
Internal address for DMA transaction
DMA length in words
DMA control
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX17xx Series
7-22