pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 334

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Figure 8:
controller
SDRAM
Controller
SDRAM
Examples of Supported Memory Configurations
DDR
DDR
3.2 Error Signaling
3.3 Latency
clk/clkn
cmd
DQ
D[31:0]
DQ[3:2]
D[31:16]
DQ[1:0]
D[15:0]
clk/clkn
cmd
The MMIO port does not support error signaling. Reads from invalid addresses return
the value “0”, writes to invalid addresses are ignored. The errors are not reported at
system level.
Changing MMIO registers of an initiated DDR SDRAM Controller may cause incorrect
behavior. Forcing the DDR controller into halt mode, programming MMIO registers
while in halt mode, then unhalting the DDR controller when the MMIO registers have
been programmed is the suggested series of actions to take.
The DDR SDRAM Controller uses two pipeline stages to calculate the command(s)
that will be issued to the DDR memories after a MTL command is accepted by the
DDR controller.
We will describe the latency of a MTL read command. Assume we have a MTL read
command on one of the MTL ports in cycle 0 which is accepted by the DDR
controller. In cycle 1, the DDR controller will determine the first DDR burst for the MTL
read command. In cycle 2, the DDR SDRAM Controller will determine the DDR
commands that need to be sent out on the DDR interface (we assume we do not have
Single Rank
SDRAM
SDRAM
SDRAM
DDR
DDR
DDR
x16
x16
x32
Rev. 1 — 17 March 2006
controller
SDRAM
Controller
SDRAM
DDR
DDR
DQ
D[31:0]
DQ[3:2]
D[31:16]
DQ[1:0]
D[15:0]
clk/clkn
cmd
clk/clkn
cmd
Two Ranks of Memories
SDRAM
SDRAM
SDRAM
DDR
DDR
DDR
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
x16
x16
x32
Chapter 9: DDR Controller
PNX17xx Series
clk/clkn
clk/clkn
cmd
cmd
SDRAM
SDRAM
SDRAM
DDR
DDR
DDR
x16
x16
x32
9-17