pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 293

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 6: Register Summary
PNX17XX_SER_1
Preliminary data sheet
0x10,4090
0x10,4094
0x10,4098
0x10,409C
0x10,40A0
0x10,40A4
0x10,40A8
0x10,40AC
0x10,40B0
0x10,40B4
0x10,40B8
0x10,40BC
0x10,40C0
0x10,40C4
0x10,40C8
0x10,40CC
0x10,40D0
0x10,40D4
0x10,40D8
0x10,40DC
0x10,40E0
0x10,40E4
0x10,40E8
0x10,40EC
0x10,40F0
0x10,40F4
0x10,40F8
0x10,40FC
0x10,4100
0x10,4FA0
0x10,4FA4
0x10,4FA8
0x10,4FAC
0x10,4FB0
0x10,4FB4
0x10,4FB8
0x10,4FBC
0x10,4FC0
Name
BASE1_PTR3
BASE2_PTR0
BASE2_PTR1
BASE2_PTR2
BASE2_PTR3
SIZE0
SIZE1
SIZE2
SIZE3
DIVIDER_0
DIVIDER_1
DIVIDER_2
DIVIDER_3
TSU0
TSU1
TSU2
TSU3
TSU4
TSU5
TSU6
TSU7
TSU8
TSU9
TSU10
TSU11
TIME_CTR
TIMER_IO_SEL
VIC_INT_STATUS
DDS_OUT_SEL
INT_STATUS0
INT_ENABLE0
INT_CLEAR0
INT_SET0
INT_STATUS1
INT_ENABLE1
INT_CLEAR1
INT_SET1
INT_STATUS2
…Continued
Description
Base address for DMA buffer 1 of FIFO queue 3.
Base address for DMA buffer 2 of FIFO queue 0.
Base address for DMA buffer 2 of FIFO queue 1.
Base address for DMA buffer 2 of FIFO queue 2.
Base address for DMA buffer 2 of FIFO queue 3.
Size of queue 0 in bytes.
Size of queue 1 in bytes.
Size of queue 2 in bytes.
Size of queue 3 in bytes.
Frequency divider for FIFO queue 0
Frequency divider for FIFO queue 1
Frequency divider for FIFO queue 2
Frequency divider for FIFO queue 3
Timestamp Unit 0.
Timestamp Unit 1
Timestamp Unit 2
Timestamp Unit 3
Timestamp Unit 4
Timestamp Unit 5
Timestamp Unit 6
Timestamp Unit 7
Timestamp Unit 8
Timestamp Unit 9
Timestamp Unit 10.
Timestamp Unit 11
31-bit timestamp master time counter. Runs at 13.5 MHz (108 MHz/8).
Selects GPIO pins or internal signals to be use as inputs for internal TM5250 timers.
Combined Interrupt status register for the VIC interrupts
Enables GPIO[14:12] pins to output clocks coming from the clock module.
Interrupt status register, combined with module status for FIFO queue 0
Interrupt enable register for FIFO queue 0
Interrupt clear register (by software) for FIFO queue 0
Interrupt set register (by software) for FIFO queue 0
Interrupt status register, combined with module status for FIFO queue 1
Interrupt enable register for FIFO queue 1
Interrupt clear register (by software) for FIFO queue 1
Interrupt set register (by software) for FIFO queue 1
Interrupt status register, combined with module status for FIFO queue 2
Rev. 1 — 17 March 2006
Chapter 8: General Purpose Input Output Pins
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
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