pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 822

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
2.3.1 Arbitration
2.1 Error Generation
2.2 Interrupt Generation
2.3 Programmable Timeout
In the total aperture range there are holes, a.k.a. “Null” modules, between the
different MMIO targets specified by noncontiguous offsets. Each hole is considered a
null target. When an offset of 0xffc within each hole is addressed, the controller will
respond with a module ID and the size of the region.
Error capture registers inside the network controller will capture the current address
and operation that was in progress when an error is reported or when a timeout
occurs. Once an error has been captured, the capture registers are no longer
updated until the interrupt is cleared.
Errors caused by TM5250 32-bit read operations are not captured , and not reported
to the TM5250. Therefore, when the currently selected initiator is the TM5250 (as
determined by the arbiter), if the operation is a read, and the mask is all ones, any
errors are blocked, including timeout errors . In this case, the capture registers are not
updated and error signals are not asserted. This is to prevent errors on speculative
loads.
The DCS network controller generate an interrupt for:
These interrupts can be enabled, cleared, software set and status seen by accessing
registers on top of the DCS network controllers MMIO space.
The timeout block uses a 17-bit counter to count clock cycles of an active transaction.
The counter increments when the select signal (sel) is high. The counter
synchronously resets to zero when sel is low.
When the timeout counter reaches a certain value determined by the control register
BC_CTRL, the counter stops incrementing and the abort_all signal is sent to the
currently selected target. Each timeout limit is a number equal to 2n-1, allowing the
timeout detection circuit to be a simple mux which selects one bit from the timeout
counter. Note that the three least significant bits of the counter are not monitored,
because no transaction can complete in less than four clock cycles.
When a timeout occurs, the abort signal is asserted to the currently selected target.
The timeout condition is also logically ORed with the DCS error input to force an error
indication back to the target.
A “round robin” arbiter is used to selective grant access to each of the requesting
initiators. The arbiter will default grant the last device that was granted. Therefore,
when no initiator is requesting access, the default grant will be given to the initiator
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Error acknowledge detected on the DCS network
DCS Network timeout
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 30: DCS Network
30-2