pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 730

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
5.8.3 Quality-of-service Transmission Mode
The two transmit descriptor/status arrays and datapaths can also be used to
implement a generic quality-of-service (QoS) mechanism for transmit packets.
The QoS mechanism distinguishes two priority queues: a queue with low priority and
a queue with high priority. The Tx descriptor FIFO (using TxDescriptor and TxStatus)
and Tx DMA manager implement the high-priority queue and the TxRt descriptor
FIFO (using TxRtDescriptor and TxRtStatus) and TxRt DMA manager implement the
low-priority queue.
To implement QoS, software should enter transmit packets that have a high quality of
service requirements into the Tx (high-priority) descriptor array, while other packets
should be entered into the TxRt (low-priority) descriptor array. If there are any packets
in the high priority queue, they are sent out first before any packets that are waiting in
the low-priority queue. Packets in the low-priority queue are only sent if the
high-priority queue is empty.
To prevent starvation of packets in the low priority queue, the QoSTimeout register
defines the maximum number of transmit clock cycles that low-priority packet must
wait at the head of the low-priority queue. An internal time-out counter starts counting
transmit clock cycles, starting from 0, as soon as a low-priority packet reaches the
transmission arbiter. If the low-priority packet is still waiting to be transmitted when
the counter reaches the QoSTimeout register’s value, then the arbiter will promote
the priority of only that one low-priority packet over the high priority queue. After
sending the low-priority packet, the low-priority queue will be set back to the low
priority. The waiting time of a packet in the low-priority queue can be larger than the
QoSTimeout register’s value if it has to wait to reach the head of the queue.
To enable the QoS mechanism, set bit EnableQoS bit in the Command register to 1.
When the QoS mechanism is active, the time-stamp word in the Tx and TxRt
descriptors is ignored, and the BlockZone register is disabled. The descriptor format
is still the same.
Rev. 1 — 17 March 2006
Chapter 23: LAN100 — Ethernet Media Access Controller
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
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