pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 468

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
1.2 FGPO to VDO pin mapping
1.3 DTL MMIO Interface
1.4 Header Initiator
1.5 Data Initiator
1.6 Record Output Mode
fgpo_start (fgpo_rec_start) maps to VDO_D[32]
fgpo_stop (fgpo_buf_start) maps to VDO_D[32]
fgpo_clk from clock module maps to VDO_C2
VDO_D[31:0] mapping depends on the VDO_MODE (Output Router) register
settings, see
This block contains all of the programmable registers used by the FGPO module
accessed through the MMIO bus. Refer to
block also handles clock domain crossing between the MMIO bus clock and the
FGPO module clock.
If either FGPO_CTL.TSTAMP_SELECT or FGPO_CTL.VAR_LENGTH bits are set
this DTL Initiator will read the record/message Timestamp and Variable Length fields.
The Variable Length information is passed on to the DMA Engine to issue a read
request from memory. The Timestamp information is passed to the Data Output
Engine for a timestamp trigger point. The MTL DTL Adapter for this DTL port contains
a 2x8 (16 byte) FIFO.
Issues main memory read requests for all data samples. The MTL DLT Adapter for
this DTL port contains a 128x8 (1024 byte) FIFO.
This mode allows the FGPO to read and transmit structured record data from main
memory to the outside world. The start of a record may be triggered by reaching an
absolute time (Timestamp), by expiration of a counted gap between records, or by a
synchronized external transition on the fgpo_rec_sync pin.
The switching of buffers may also be triggered by a synchronized external transition
on the fgpo_buf_sync pin.
A record start control signal is generated at the start of each record on the fgpo_start
(fgpo_rec_start) pin.
Output starts from a new location in the buffer for each record. Successive records
are output until the programmed number of records in a buffer is exhausted, then the
alternate buffer is used.
A buffer start control signal is generated at the start of each new buffer on the
fgpo_stop (fgpo_buf_start) pin.
This allows the output of video frames consisting of multiple line records,
synchronized by a frame or field synchronization signal.
Chapter 3 System On Chip
Rev. 1 — 17 March 2006
Chapter 13: FGPO: Fast General Purpose Output
Resources.
Section 4.
for registers description. This
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
13-3