pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 514

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 1: Audio Out Unit External Signals
[1]
PNX17XX_SER_1
Preliminary data sheet
Signal
Name
AO_OSCLK
AO_SCK
AO_WS
AO_SD[0]
AO_SD[1]
AO_SD[2]
AO_SD[3]
These signals are external to the chip, after the pad cells.
Type
OUT
OUT
OUT
OUT
OUT
I/O
I/O
Description
Oversampling
intended for use as the 256 Fs or 384 Fs oversampling clock by the external D/A conversion
subsystem.
Serial
default), SCK acts as input. It receives the Serial Clock from the external audio D/A subsystem. The
clock is treated as fully asynchronous to the chip main clock.
When Audio Out is programmed to act as serial interface timing master, SCK acts as output. It
drives the Serial Clock for the external audio D/A subsystem. The clock frequency is a
programmable integral divide of the OSCLK frequency.
SCK is limited to the frequency of the OSCLK or lower.
Word
WS acts as an input. WS is sampled on the opposite SCK edge at which SD is asserted.
When Audio Out is programmed as serial-interface timing master, WS acts as an output. WS is
asserted on the same SCK edge as SD.
WS is the word select or frame synchronization signal from/to the external D/A subsystem. Each
audio channel receives one sample for every WS period.
WS can be set to change on OSCLK positive or negative edges by the CLOCK_EDGE bit.
Serial Data for channel
change on OSCLK positive or negative edges by the CLOCK_EDGE bit.
Serial Data for channel
change on OSCLK positive or negative edges by the CLOCK_EDGE bit.
Serial Data for channel
change on OSCLK positive or negative edges by the CLOCK_EDGE bit.
Serial Data for channel
change on OSCLK positive or negative edges by the CLOCK_EDGE bit.
The OSCLK output is an accurate, programmable clock output intended to be used
as the master system clock for the external D/A subsystem. The other pins constitute
a flexible serial output interface.
Using the Audio Out MMIO registers, these connectors can be configured to operate
in a variety of serial interface framing modes, including but not limited to:
Select. When Audio Out is programmed as the serial-interface timing slave (RESET default),
Clock. When Audio Out is programmed to act as the serial interface timing slave (RESET
•
•
SCK - Serial Clock
WS - Word Select
SD[3:0] - Serial Data
Standard stereo I
frame). For further details on I
1996, in the Multimedia ICs Data Handbook IC22 by Philips
Semiconductors, 1998.
LSB first with 1- to 16-bit data per channel
0 = Left Channel
1 = Right Channel
Clock. This output can be programmed to emit any frequency up to 40 MHz. It is
[1]
1. Connect to stereo external audio D/A subsystem. SD[0] can be set to
2. Connect to stereo external audio D/A subsystem. SD[1] can be set to
3. Connect to stereo external audio D/A subsystem. SD[2] can be set to
4. Connect to stereo external audio D/A subsystem. SD[3] can be set to
Rev. 1 — 17 March 2006
2
S (MSB first, one bit delay from WS, left and right data in a
2
S, refer to the “I
2
S Bus Specification” dated June 5
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 15: Audio Output
15-3