pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 280

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Monitoring continues in DMA buffer 2, until it fills up. At that time,
INT_STATUSx.BUF2_RDY is asserted, monitoring continues in the new DMA buffer
1, and the interrupt needs to be acknowledged as for DMA buffer 1.
If the software fails to read the full DMA buffers in time (i.e BUF1_RDY or BUF1_RDY
is not cleared in time), the overrun error flag, INT_STATUSx.FIFO_OE, is raised and
data may be lost. The INT_STATUSx.FIFO_OE error flag can only be cleared by an
explicit write of ‘1’ to the INT_CLEARx.FIFO_OE_CLR bit. The interrupt if seen by the
TM5250 CPU if the bit INT_ENABLEx.FIFO_OE_EN is set.
If enabled, an interval of silence, GPIO_EVx.INTERVAL, can cause a BUFx_RDY flag
to be asserted before all locations in the DMA buffer have been filled. Therefore,
whenever BUFx_RDY is asserted, software is required to read the relevant
INT_STATUSx register to know exactly how many valid 32-bit words of data are in the
DMA buffer. The INT_STATUSx holds the VALID_PTR field which gives this
information.
The number of valid 32-bit data words written to the DMA buffers is loaded by the
GPIO module to the VALID_PTR field of the INT_STATUSx register immediately
before the GPIO sets the relevant BUFx_RDY flag. If a second BUFx_RDY is
activated before the first flag was cleared, VALID_PTR cannot be updated by the
GPIO until the first activated BUFx_RDY flag is cleared by software. This clear will
allow the GPIO to load the new VALID_PTR value for the second buffer.
If both BUFx_RDY flags are cleared at the same time, i.e if the value of VALID_PTR is
not needed, the VALID_PTR value points back to the first buffer whose BUFx_RDY
flag was raised. If the VALID_PTR value is required to be read, each BUFx_RDY
must be cleared individually and in the correct order.
VALID_PTR is stable to be read by software when a BUFx_RDY flag is raised.
BASE1_PTRx should be stable to be loaded by the GPIO module when BUF1_RDY
is cleared by software and BASE2_PTRx should be stable to be loaded by the GPIO
module when BUF2_RDY is cleared by software.
Remark: A DMA buffer can ‘fill up’ in two ways: all available locations are written to,
or, in monitoring timestamped event mode, an interval of silence occurred.
Remark: SIZE must be a multiple of 64 bytes. SIZE is a static configuration register
and should not change during GPIO operation.
The Interval of Silence in Event Timestamping Sampling Mode
If events occur on a monitored signal and an interval of silence follows, the relevant
internal buffer contents are flushed to the DMA buffers.
When the contents of the internal buffer are flushed to the DMA buffer the relevant
BUFx_RDY flag is set. The BUFx_RDY interrupt indicates that the DMA buffer is
ready to be read by software and writing is switched to the second DMA buffer.
When an interval of silence occurs all the 64 bytes of the internal buffer are flushed
even though there may not be 64 bytes of valid data in the internal buffer. Software
must then read the module status to read the address where the last valid 32-bit data
word, INT_STATUSx.VALID_PTR, was written.
Rev. 1 — 17 March 2006
Chapter 8: General Purpose Input Output Pins
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
8-9