pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 249

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 9: Registers Description
PNX17XX_SER_1
Preliminary data sheet
Bit
8
7:4
3:0
Offset 0x04 003C
31:16
15:8
7:0
Offset 0x04 0040
31:16
15:0
Offset 0x04 0044
31:16
15:0
Offset 0x04 0048
31:8
7:0
Offset 0x04 004C
31:24
23:16
15:8
7:0
Offset 0x04 0050
31:21
Symbol
Reserved
gppm_cmd
gppm_ben
Reserved
unlock_ssid
unlock_setup
device_id
vendor_id
status
command
class code
revision id
BIST
Header Type
latency timer
cache line size
Base Address 10
Unlock Register
Image of Device ID and Vendor ID
Image of Command/Status
Image of Class Code/Revision ID
Image of Latency Timer/Cache Line Size
Base Address 10 Image
Acces
s
R
R/W
R/W
R
W
W
R
R
R
R/W*
R/W*
R
R
R
R/W*
R/W*
R/W*
Value
0
0
0
0
0
0
0x5406
0x1131
0x0290
0x0000
048000
0
0
0
0
0
0
Rev. 1 — 17 March 2006
Description
Command to be used with PCI cycle. Acceptable commands to use
in the command field include IO read, IO write, memory Read,
memory Write, configuration read and interrupt acknowledge. If
configuration management is enabled, configuration write may be
used.
Byte enables to be used with PCI cycle
Writing a “0xCA” to this field will unlock the “subsystem_id” and
“subsystem_vendor” registers. A writer to the subsystem_id/
subsystemvendor” register will lock the register again.
Writing a “0xCA” to this field will unlock the “classcode”,
“max_latency”, “min_gnt” and “pci_setup” registers. A write to the
“pci_setup” register to lock registers again.
PCI configuration device ID
PCI configuration vendor ID
PCI configuration status register
PCI configuration command register.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
Refer to configuration register 4 for details on which bits are
implemented and controllable.
PCI configuration class code.
*Write-once/Read-only
PCI configuration revision ID
PCI configuration BIST
PCI configuration Header Type
PCI configuration latency timer.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
PCI configuration cache line size.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
PCI configuration Base address for DRAM.
This register affects the decode and routing of the bus controllers. It
should not be relied on as stable for 10 clocks after writing.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX17xx Series
7-28