EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 770
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Device Configuration Pins
11–52
Stratix Device Handbook, Volume 2
nIO_PULLUP
MSEL
nCONFIG
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device
Pin Name
[2..0]
N/A
N/A
N/A
User Mode
All
All
All
Configuration
Scheme
Input
Input
Input
Pin Type
Dedicated input that chooses whether the
internal pull-ups on the user I/Os and dual-
purpose I/Os (
RDYnBSY
INIT_DONE
off before and during configuration. A logic high
(1.5-V, 1.8-V, 2.5-V, 3.3-V) turns off the weak
internal pull-ups, while a logic low turns them
on.
The
V
resistor that is always active.
3-bit configuration input that sets the Stratix or
Stratix GX device configuration scheme. See
Table 11–2
These pins can be connected to V
I/O bank they reside in or ground. This pin uses
Schmitt trigger input buffers.
Configuration control input. Pulling this pin low
during user-mode causes the FPGA to lose its
configuration data, enter a reset state, tri-state
all I/O pins. Returning this pin to a logic high
level initiates a reconfiguration.
If your configuration scheme uses an
enhanced configuration device or EPC2
device,
to the configuration device’s
pin. This pin uses Schmitt trigger input buffers.
C C I N T
nIO_PULLUP
nCONFIG
and has an internal 2.5 k pull-down
,
nCS
for the appropriate connections.
,
DEV_OE
DATA[7..0]
,
CS
Description
can be tied directly to V
,
input buffer is powered by
RUnLU
(Part 2 of 8)
,
DEV_CLR
Altera Corporation
,
PGM[]
nINIT_CONF
,
nWS
) are on or
C C I O
,
,
nRS
CLKUSR
July 2005
of the
,
C C
or
,
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