EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 544

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Software Support
Figure 5–45. SERDES Bypass LVDS Receiver Using M512 RAM Block as the Deserializer
Figure 5–46. SERDES Bypass LVDS Transmitter Using M512 RAM Block as Deserializer
5–72
Stratix Device Handbook, Volume 2
rx_inclk
core_data
core_clk
RXp
RXn
inclock
RX_PLL
datain[0]
inclock
inclock
÷1 clock1
×2 clock0
DDIO In
RX_PLL
dataout_h[0]
dataout_l[0]
÷1 clock1
÷2 clock0
clock
clock
W-UpCounter
R-UpCounter
q[2..0]
q[5..0]
clock
clock
W-UpCounter
R-UpCounter
datain[7..0]
waddr[5..0]
wclock
raddr[7..0]
rclock
q[4..0]
q[2..0]
Simple Dual Port ×2×8
TX_SESB
512 Bits
dataout[7..0]
raddr[5..3]
GND
datain[1..0]
waddr[7..0]
wclock
raddr[5..0]
rclock
waddr[7..5]
V
CC
Simple Dual Port
datain_h[0]
datain_l[0]
outclock
datain_h[0]
datain_l[0]
outclock
RX_SESB
512 Bits
DDIO Out
RX_PLL
dataout[7..0]
dataout_h[0]
dataout_l[0]
Altera Corporation
/1 clock1
/2 clock0
July 2005
waddr[7..5]
Core data
raddr[5..3]
Core clock
TXp
TXn
tx_outclk