EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 710

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

I/O Structure
10–26
Stratix Device Handbook, Volume 2
f
f
For more information on external RAM interfacing, see the Stratix Device
Family Data Sheet section of the Stratix Device Handbook, Volume 1 or the
Stratix GX Device Family Data Sheet in the Stratix GX Device Family
Handbook, Volume 1.
I/O Standard Support
The Stratix and Stratix GX devices support all of the I/O standards that
APEX II and APEX 20K devices support, including high-speed
differential I/O standards such as LVDS, LVPECL, PCML, and
HyperTransport
clocks, and differential SSTL on output clocks. Stratix and Stratix GX
devices also introduce support for SSTL-18 Class I & II. Similar to APEX II
devices, Stratix and Stratix GX devices only support certain I/O
standards in designated I/O banks. In addition, vref pins are dedicated
pins in Stratix and Stratix GX devices and now support up to 40 input
pins.
For more information about I/O standard support in Stratix and
Stratix GX devices, see the Selectable I/O Standards in Stratix &
Stratix GX Devices chapter.
High-Speed Differential I/O Standards
Stratix and Stratix GX devices support high-speed differential interfaces
at speeds up to 840 Mbps using high-speed PLLs that drive a dedicated
clock network to the SERDES. Each fast PLL can drive up to 20 high-
speed channels. Stratix and Stratix GX devices use enhanced PLLs and
M512 RAM blocks to provide up to 420 Mbps performance for SERDES
bypass clock interfacing. There is no restriction on the number of
channels that can be clocked using this scenario.
Stratix and Stratix GX devices have a different number of differential
channels than APEX II devices.
number of differential channels supported in Stratix and Stratix GX
devices.
EP1S10
Table 10–9. Number of Dedicated DIfferential Channels in Stratix Devices
(Part 1 of 2)
Device
Note (1)
TM
Pin Count
technology, differential HSTL on input and output
672
780
Number of Receiver
Tables 10–9
Channels
36
44
and
10–10
Transmitter Channels
highlight the
Altera Corporation
Number of
36
44
July 2005