EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 457

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 4–20. Differential Termination
Altera Corporation
June 2006
Transmitter
Differential
For more information on termination for voltage-referenced I/O
standards, see the Selectable I/O Standards in Stratix & Stratix GX Devices
chapter in the Stratix Device Handbook, Volume 2; or the Stratix GX Device
Handbook, Volume 2.
Differential I/O Standards
Differential I/O standards typically require a termination resistor
between the two signals at the receiver. The termination resistor must
match the differential load impedance of the bus. Stratix and Stratix GX
devices provide an optional differential termination on-chip resistor
when using LVDS.
See the High-Speed Differential I/O Interfaces in Stratix Devices chapter for
more information on differential I/O standards and their interfaces.
For differential I/O standards, I/O banks support differential
termination when V
Differential Termination (R
Stratix devices support differential on-chip termination for source-
synchronous LVDS signaling. The differential termination resistors are
adjacent to the differential input buffers on the device. This placement
eliminates stub effects, improving the signal integrity of the serial link.
Using differential on-chip termination resistors also saves board space.
Figure 4–20
Stratix GX devices.
shows the differential termination connections for Stratix and
Selectable I/O Standards in Stratix & Stratix GX Devices
CCIO
Z 0
Z 0
equals 3.3 V.
D
)
Stratix Device Handbook, Volume 2
Differential On-Chip Termination
Receiver Buffer with
R
D
Stratix LVDS
4–29