EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 732

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Configuration Schemes
11–14
Stratix Device Handbook, Volume 2
Table 11–7
configuration.
PS Configuration with a Download Cable
In PS configuration with a download cable, an intelligent host transfers
data from a storage device to the Stratix or Stratix GX device through the
MasterBlaster, USB-Blaster, ByteBlaster II or ByteBlasterMV cable. To
initiate configuration in this scheme, the download cable generates a
low-to-high transition on the nCONFIG pin. The programming hardware
then places the configuration data one bit at a time on the device’s DATA0
pin. The data is clocked into the target device until CONF_DONE goes high.
The CONF_DONE pin must have an external 10-k pull-up resistor in
order for the device to initialize.
When using programming hardware for the Stratix or Stratix GX device,
turning on the Auto-Restart Configuration on Frame Error option does
not affect the configuration cycle because the Quartus II software must
restart configuration when an error occurs. Additionally, the Enable
User-Supplied Start-Up Clock (CLKUSR) option has no affect on the
device initialization since this option is disabled in the SOF when
programming the FPGA using the Quartus II software programmer and
a download cable. Therefore, if you turn on the CLKUSR option, you do
not need to provide a clock on CLKUSR when you are configuring the
FPGA with the Quartus II programmer and a download cable.
Figure 11–5
using a MasterBlaster, USB-Blaster, ByteBLaster II or ByteBlasterMV
cable.
Notes to
(1)
(2)
DATA0
DATA[7..1]
I/O Pins
Table 11–7. DATA Pin Status Before & After Configuration
The status shown is for configuration with a configuration device.
The function of these pins depends upon the settings specified in the Quartus II
software using the Device & Pin Option dialog box (see the Software Settings
section in the Configuration Handbook, Volume 2, and the Quartus II Help software
for more information).
(1)
Pins
Table
shows the status of the device DATA pins during and after
shows PS configuration for the Stratix or Stratix GX device
11–7:
(2)
Used for configuration
Used in some configuration modes User defined
Tri-state
During
Stratix or Stratix GX Device
User defined
User defined
Altera Corporation
After
July 2005