EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 751

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 11–17. PPA Multi-Device Configuration Circuit
Notes to
(1)
(2)
Altera Corporation
July 2005
If not used, you can connect the CS pin to V
Connect the pull-up resistor to the same supply voltage as the Stratix or Stratix GX device.
Address Decoder
ADDR
Microprocessor
Figure
ADDR
11–17:
Memory
DATA[7..0]
10 k
V
Ω
CC
You can also use PPA mode to configure multiple Stratix and Stratix GX
devices. Multi-device PPA configuration is similar to single-device PPA
configuration, except that the Stratix and Stratix GX devices are cascaded.
After you configure the first Stratix or Stratix GX device, nCEO is asserted,
which asserts the nCE pin on the second device, initiating configuration.
Because the second Stratix or Stratix GX device begins configuration
within one write cycle of the first device, the transfer of data destinations
is transparent to the microprocessor. All Stratix and Stratix GX device
CONF_DONE pins are tied together; therefore, all devices initialize and
enter user mode at the same time. See
(3)
V
CC
10 k
(2)
Ω
10 k
V
Ω
CC
DATA[7..0]
nCS
CS (1)
CONF_DONE
nSTATUS
nWS
nRS
nCONFIG
RDYnBSY
CC
(2)
Stratix Device 1
directly. If not used, the nCS pin can be connected to GND directly.
MSEL2
MSEL1
MSEL0
nCEO
DCLK
nCE
GND
GND
V
CC
V
CC
Configuring Stratix & Stratix GX Devices
10 k
(2)
Ω
Figure
Stratix Device Handbook, Volume 2
DATA[7..0]
nCS
CS (1)
CONF_DONE
nSTATUS
nCE
nWS
nRS
nCONFIG
RDYnBSY
11–17.
Stratix Device 2
MSEL2
MSEL1
MSEL0
nCEO
DCLK
V
CC
N.C.
10 k
GND
(2)
Ω
V
CC
11–33